A Samsung executive has projected that high-bandwidth memory (HBM) will consume nearly 30% of global DRAM wafer capacity next year, with the company framing the reallocation as an accelerator of an existing squeeze on conventional memory supply.

The figure is among the highest publicly disclosed HBM-capacity shares from a major DRAM manufacturer and signals a more aggressive HBM ramp than the industry has previously communicated to buyers.

How does HBM consume capacity differently?

HBM is a stacked DRAM product category built for AI accelerators and high-end GPUs. Conventional DRAM modules place a single DRAM die in each package, with the memory controller handling data transfer through motherboard traces.

HBM instead assembles four, eight, or twelve DRAM dies vertically inside one package, connecting them through through-silicon-via (TSV) interconnects and bonding the stack to a base logic die through microbumps.

The architecture delivers aggregate bandwidth in the terabyte-per-second range per stack — roughly an order of magnitude above the per-channel bandwidth of DDR5 modules.

That bandwidth advantage comes at a cost in silicon area: each HBM die occupies substantially more wafer space than an equivalent-capacity DDR5 or LPDDR5 die. The additional TSV formation, microbump bonding, and stack-assembly steps also extend cycle time beyond conventional DRAM packaging.

What does the reallocation accelerate?

A projected 30% allocation of wafer capacity to HBM therefore reduces the silicon available for commodity DRAM by a factor larger than 30%. Conventional categories — server DDR4 and DDR5, mobile LPDDR4X and LPDDR5X, graphics GDDR6, and emerging GDDR7 — all share fabrication lines with HBM on advanced 1a, 1b, and 1c process nodes. Every wafer diverted to HBM stacking removes output from those product lines.

The Samsung projection implies the capacity shift toward HBM will deepen in the next calendar year rather than stabilize. With approximately 70% of global DRAM wafer capacity remaining for all non-HBM products combined, conventional DRAM buyers face tighter allocation conditions than the headline percentage alone indicates.

The squeeze extends across multiple segments that share fabrication nodes with HBM. Yield management, packaging throughput, and TSV line capacity all bind together when a larger fraction of wafers is funneled into HBM stacking rather than standard DRAM packaging. Server OEMs planning DDR5 rollouts, PC manufacturers preparing next-generation platforms, and smartphone brands specifying the latest LPDDR generations will all compete for the remaining capacity.

What remains unclear about the projection?

The Samsung statement does not specify whether the 30% figure is measured at the wafer-start level or the bit-shipment level, nor which HBM generations — HBM2E, HBM3, HBM3E, or HBM4 — the figure includes. The reporting also does not clarify whether the projection refers to Samsung's captive capacity, the industry's aggregate, or a specific market segment.

Despite those gaps, the headline figure sets a benchmark for industry planning: roughly one-third of global DRAM fabrication capacity is on track to be absorbed by a single product category within 12 months. Conventional memory supply has rarely been so concentrated on a non-substitute use case.

For procurement teams and OEMs, the projection reinforces a planning environment in which conventional DRAM contracts must be negotiated further in advance, at higher floor prices, and with stricter allocation clauses than during the prior memory cycle.