Samsung expects high-bandwidth memory (HBM) to consume nearly 30% of the global DRAM industry's production capacity by 2027, up from approximately 20% today, according to TrendForce reporting.

The 10-percentage-point rise over the next two to three years reflects the company's projection of accelerating demand for AI accelerators and high-end GPUs. These workloads require HBM stacks to feed their parallel compute pipelines at bandwidth levels that conventional DDR modules cannot deliver.

What does the 30% target signal?

Allocating nearly one-third of industry capacity to HBM means stacked memory will draw wafer output away from conventional DDR4 and DDR5 modules. HBM commands premium pricing because of through-silicon-via (TSV) processing, multi-die stacking, and tighter thermal envelopes required by accelerator co-designs.

For the broader DRAM market, the implication is a tighter supply of commodity parts. As a larger share of wafers feeds HBM production lines, less capacity remains for standard PC and server DRAM at the 1z and 1a process nodes.

End customers building AI servers typically consume multiple HBM stacks per accelerator, multiplying the wafer footprint of every shipped GPU.

HBM's higher per-bit pricing also reshapes memory-maker revenue mix. Even modest shifts in allocation toward HBM can lift consolidated DRAM revenue more than underlying bit-shipment growth would suggest, because HBM bits sell at multiples of DDR bit prices.

Which suppliers does this affect most?

HBM is produced primarily by Samsung, SK hynix, and Micron. As the largest of the three by capacity, Samsung's projection carries weight for the wider supply chain, including foundry partners such as TSMC and back-end packaging houses handling silicon interposer and chip-on-wafer-on-substrate (CoWoS) work.

Equipment makers — ASML, Applied Materials, and Tokyo Electron among them — read these capacity-mix signals as forward indicators for tool orders. A heavier HBM mix typically pulls more deposition, etch, and bonding-tool demand per wafer than commodity DRAM, because of the additional mask layers and the back-end stacking flows.

How could the shift move DRAM pricing?

Reallocating 30% of capacity to HBM compresses conventional DRAM supply and typically lifts average selling prices (ASPs) for DDR4 and DDR5. Contract pricing responds with a lag, but spot-market availability tightens immediately when allocation ratios shift.

If SK hynix and Micron adopt similar allocation targets, the industry-wide migration could tighten the DDR market more sharply, especially in the densities and process-node tiers that feed PC and mainstream server modules. Memory buyers planning 2027 platform roadmaps will watch these allocation moves closely.

What remains unclear

The full TrendForce report — including the venue where Samsung executives disclosed the projection, the exact 2027 baseline date, and any breakdown by HBM generation — was not captured in the circulated headline summary. Die Signal has requested additional details from Samsung and TrendForce.

Samsung has not publicly commented on the TrendForce summary. Neither SK hynix nor Micron has issued a statement addressing the projected 30% allocation, leaving peer-response scenarios open.

For now, the headline number points to one clear direction: HBM's share of DRAM wafer capacity will continue to expand, and the rest of the DRAM market will absorb the consequences.