Samsung projects that High Bandwidth Memory (HBM) will absorb 30 per cent of its DRAM wafer capacity by 2027, according to a publication citing the memory maker. The 30 per cent wafer-commitment figure represents a step-change in product mix for a company that has spent most of the last decade allocating the bulk of its fabs to commodity DDR memory.

The shift follows sustained pull from AI accelerator manufacturers. Nvidia's H100, H200, and B-series GPUs consume multiple HBM stacks per device. Custom hyperscaler ASICs from AMD, Broadcom, and direct hyperscaler buyers add parallel demand across data-center build-outs.

What share is HBM taking from the DRAM mix?

The 30 per cent figure applies to wafer capacity, not finished-die output. Samsung's stated 2027 benchmark commits a specialty product line to nearly a third of its fab throughput at a scale not previously disclosed by the company. Trade-press estimates in earlier years placed HBM's share of total DRAM wafer allocation in the low single digits.

Wafer share differs from revenue share. HBM commands per-bit pricing multiples of standard DDR5, so 30 per cent of wafer starts could yield a substantially larger share of DRAM revenue.

Why does this wafer share matter for supply chains?

Conventional DDR5 and LPDDR5 remain the volume backbone of the DRAM market. Earmarking nearly a third of wafer starts for HBM tightens availability of standard DRAM products through 2027 unless Samsung, SK hynix, and Micron collectively expand aggregate fab capacity. Procurement teams for server and PC OEMs could see lead times extend further.

SK hynix has historically led the HBM segment, supplying Nvidia's flagship accelerators. Micron entered HBM3E volume production in 2024. Samsung's 30 per cent target suggests a push to close that share gap, though the company disclosed no unit volume or revenue figure tied to the wafer share.

Why is HBM the binding constraint for AI silicon?

HBM stacks multiple DRAM dies vertically through through-silicon vias, delivering bandwidth measured in terabytes per second per stack. Current-generation HBM3E ships in 8-high and 12-high configurations. HBM4, slated for 2025–2026 volume ramps, introduces 16-high stacks and per-stack capacities above 30 GB. The architecture is purpose-built for GPU and ASIC accelerators.

The recurring chokepoint in AI server build-outs is not GPU silicon itself but the supply of HBM stacks feeding the package. TSMC's CoWoS advanced-packaging line adds a second gating layer downstream.

What questions remain open?

• Whether the 2027 figure covers HBM3E only or includes HBM4 volume.
• The unit split between 8-high, 12-high, and 16-high stacks within the wafer plan.
• How SK hynix and Micron will adjust capex roadmaps in response.
• Whether the 30 per cent figure is specific to Samsung's manufacturing or extrapolated to industry output.

If Samsung reaches 30 per cent wafer allocation by 2027, industry HBM bit supply could roughly double relative to 2024 levels across the three suppliers combined, easing one of the recurring supply chokepoints cited by hyperscaler buyers. Samsung did not specify the venue or date of the projection in the available reporting.