Qualcomm Validates HBC Test Chip With 18× Bandwidth Claim

Qualcomm says its first HBC test chip delivers 18× the effective bandwidth of external LPDDR5X. The company also claims more than 5× the bandwidth per watt of HBM4. It has not disclosed absolute bandwidth figures.

The result establishes functional silicon for a memory-compute design Qualcomm plans to commercialize for AI inference servers, but it does not establish commercial performance.

A compute die sits below the memory stack

Qualcomm calls the technology “High Bandwidth Computing,” or HBC. On the 2nd, local time, the company reported the result at its San Diego laboratory. The first-generation test chip passed its first hardware validation. Read, write and near-memory computing functions worked normally on physical silicon.

HBC stacks several layers of LPDDR, the low-power DRAM used in smartphones and other devices, above an AI compute die. The die receives data directly from the memory above it. It performs much of the calculation needed to generate AI responses. It then passes only the results to the main external compute chip.

That arrangement effectively places a workbench inside a storage warehouse, rather than carrying every stored item to a separate workshop before any useful processing can begin.

Conventional AI servers place HBM beside a graphics processing unit. The GPU pulls stored data from HBM for computation. HBC shortens the distance data travels. Qualcomm says the shorter path saves time and power.

What does this change for AI server designers?

For AI server designers, HBC changes where part of the inference workload runs. Much of the computation happens directly beneath the memory stack. Data can reach the nearby compute die without first making the full trip to an external GPU.

Qualcomm is targeting inference, where AI generates responses piece by piece. Even with sufficient compute power, a chip can wait for data from memory. HBC seeks to reduce that bottleneck beside the memory stack.

It could also reduce reliance on HBM and expensive packaging. Conventional HBM systems use CoWoS or EMIB to connect the memory stack, compute die and controller. They do so through an ultra-wide interface.

By doing more work below the memory, HBC needs less communication bandwidth with the main compute chip. This could reduce package cost and complexity.

Industry observers say HBC could use relatively cheaper conventional two-dimensional organic substrates instead. They also cite LPDDR5X dies, rather than HBM-specific DRAM, as a potential source of cost savings.

Qualcomm wants to enter a server AI market dominated by Nvidia and AMD. Its approach competes through a different chip structure, not a conventional GPU-centered HBM arrangement.

This matters because inference demand can remain constrained by data movement even when operators have enough accelerator compute, while HBM stacking and advanced packaging costs continue to climb.

Dragonfly sampling moves from 2027 to 2028

• First half of 2027: Qualcomm plans to sample the Dragonfly AI250 inference accelerator using HBC.
• 2028: Qualcomm plans to sample the next-generation Dragonfly AI300 with second-generation HBC.

The AI300 targets 54× the effective memory bandwidth of the LPDDR5X-based AI200. The announced milestones cover sampling, not volume shipments. No mass-production date appears in the schedule.

The announced roadmap pairs a 2027 AI250 sampling target with a second-generation AI300 in 2028, while leaving mass-production timing and broader product details remain unspecified.

Why HBM is unlikely to disappear

Futurum cautioned that the test alone does not prove actual server performance. It also does not establish economical mass-production yields.

Assessments suggest HBC is unlikely to replace HBM fully. HBC shows strength in the response-generation phase, where systems repeatedly fetch data from memory. GPU compute remains important during the reading and analysis of queries. A division of roles between HBC and GPU-HBM systems appears inevitable.

Three hurdles stand between the test chip and wider commercial adoption:

• Proven performance in real inference workloads.
• Economical mass-production yields.
• A sufficiently supported software ecosystem.

Functional silicon establishes only the first stage of validation, leaving the architecture's eventual market role contingent on measured server behavior, repeatable production economics and broad software support.

Samsung and SK Hynix supply LPDDR

If HBC proves necessary and enters mass production, South Korean memory makers could gain a larger role. Samsung Electronics and SK Hynix produce the LPDDR used in HBC as main products. Qualcomm said it is conducting supply cooperation with both companies for commercialization.

Industry observers speculate that TSMC could support technology integration and advanced packaging. No specific production-cooperation structure has been officially confirmed.

Supplier demand could therefore rise before the architecture's server economics and software support are fully settled, leaving the final manufacturing chain and allocation of production responsibilities unresolved.

What the validation establishes

The validation confirms that HBC can perform reads, writes and near-memory computation on a working chip. It does not demonstrate that the design will outperform HBM systems in deployed servers.

Qualcomm now has a functional test chip, two announced sampling milestones and proposed supply relationships. Its wider ambition is to reduce data movement, HBM dependence and packaging complexity at the same time.

The practical result will come from server workload tests, production yields, packaging costs and software adoption, rather than from the San Diego laboratory validation alone.