Qualcomm claims its HBC technology delivers six times the bandwidth per watt of conventional HBM, according to a report published by Wccftech. The figure targets the single largest bottleneck in AI accelerator design: memory bandwidth per watt.

The claim rests on where HBC places the processor. Instead of sitting beside DRAM packages on a substrate, compute dies sit directly beneath the DRAM stack. Shorter interconnects cut the energy cost of every byte moved between memory and logic.

What problem does HBC attack?

AI inference and training workloads are increasingly limited not by raw compute, but by the rate at which data reaches the compute units — the so-called memory wall. HBM stacks already place DRAM close to accelerators, but they remain separate packages with a defined interface cost in power and latency.

HBC collapses that distance. By integrating logic underneath the memory itself, Qualcomm aims to move data across far shorter paths at a claimed 6x improvement in bandwidth per watt over HBM.

For datacenter operators, bandwidth per watt translates directly into operating cost: every joule saved per gigabyte moved lowers the total cost of running large language models and other memory-intensive workloads.

Why does stacking order matter?

Conventional HBM places the memory stack on an interposer next to the GPU or ASIC. HBC inverts the arrangement, embedding compute beneath the DRAM layers. The physical change reduces wire length between storage and processing, which reduces signal energy and increases the feasible data rate.

The 6x bandwidth-per-watt figure is the headline specification Qualcomm puts forward against existing HBM implementations. Wccftech reports the claim as part of Qualcomm's push against the AI memory wall.

What comes next?

Qualcomm has not yet published a full product roadmap around HBC in the reported material, and independent validation of the 6x figure remains outstanding. The claim nonetheless signals where the next competitive front in AI silicon lies: not more FLOPS, but more bytes per watt.

Six times the bandwidth per watt, if it holds, would reset the efficiency baseline for AI memory.