Hybrid Bonding Below 5 µm Pushes Inspection Tools to 50 nm Limits

By Marcus Bennett

Defect inspection requirements for leading-edge hybrid bonding now reach down to 50 nm, and at interconnect pitches approaching 5 µm and below, that requirement is breaking the limits of conventional metrology. Particles, surface contamination and nanometer-scale topography variation can kill a bond outright, and tools must separate those yield-killing defects from harmless variation. No single technique today covers all of them.

Hybrid bonding replaces 35 µm off-chip microbumps with pad-to-pad interconnects of 10 µm pitch or smaller directly on-chip. Production levels currently sit at 4 to 9 µm. The process joins silicon-to-silicon, as in DRAM-DRAM bonding for future HBM devices, or even dissimilar stacks such as GaN-on-silicon. It runs on wafer-to-wafer or die-to-wafer platforms, cuts signal delay to negligible levels, enables thinner packages, and consumes significantly less power.

What does this change for inspection and metrology? It imposes some of the most stringent requirements ever placed on a semiconductor process, with tools resolving critical defects smaller than 100 nm while buried at the bond interface.

Why particles dominate the risk list

"Particles and surface contamination are among the most critical defects in hybrid bonding, as they can prevent contact between bonding surfaces and lead to the formation of voids," said Burhan Ali, product marketing director at Onto Innovation. "Smaller interconnect pitches reduce the tolerance for defects, making even nanoscale particles capable of causing bonding voids. For leading-edge hybrid bonding processes, defect size requirements can be as low as 50 nm."

Even a single particle can delaminate the top wafer from the one below, resulting in catastrophic failure. Cracks, delamination, overlay errors, roughness, CMP defects and warpage all threaten bond quality.

Four process steps set the metrology agenda

Bond performance depends on four processes: surface planarization, surface activation, precision alignment and thermal bonding. Chemical-mechanical polishing must control copper-pad recess to nanometer scale while keeping surface roughness at 0.5 nm RMS. Otherwise, dielectric-to-dielectric voids form during bonding.

The flow is fixed. After the wafer reaches final BEOL, a dielectric (SiCN or SiO2) is deposited and etched, barrier and copper seed layers are deposited, and copper plating fills typically square pads. Copper CMP polishes the overburden to slight dishing of several nm; the gap fills during annealing at 350° C for two hours, when copper expands to form permanent Cu-Cu and dielectric-dielectric bonds after plasma activation, hydration and face-to-face contact.

After CMP, copper pads sit recessed just 2 nm to 5 nm below the dielectric, and process control must hold this within 2 nm across the wafer.

What does pre-bond inspection look like?

Macro-inspection first catches scratches, large particles and edge damage, mapping every wafer in the lot. "By inspecting 100% of the wafers at each mask level, our macro-inspection tool provides a great complement to the micro-inspection tools on the market," said Errol Akomer, applications director at Microtronic. Slow micro tools sample only two to five wafers per lot, he noted, and "in some applications, like data center or aerospace, the customers may select only the best chips that come out of the lot," discarding the marginal ones he calls "the walking wounded."

Automated optical inspection follows cleaning. Darkfield modes collect scattered light and excel at particles and scratches; brightfield collects reflected light and isolates slurry residue, pattern defects and surface damage.

For topography, the toolset splits by scale. "Interferometric technologies are generally applicable to measure wafer-level or die-level planarity, while OCD and AFM are the best approaches for enabling extremely fine control of just a few nanometers local height variations," said Maruko Wu, senior director of product marketing at Onto Innovation. Bruker, KLA, Onto Innovation and Zygo supply white-light and phase-shifting interferometry tools, some with double-sided capability.

AFM measures roughness, dishing and protrusion at nanometer to sub-nanometer resolution. Atomic force profilometry complements it with large-area scans up to 33 × 26 mm, including the bevel edge, and can reveal out-of-spec topography even when local AFM scans confirm in-spec roughness and recess. Zeiss is also correcting planarity by inducing local strain in the wafer before backside thinning — an approach drawing interest for multi-layer stacked HBM die, according to Thomas Rodgers, senior director of market strategy at Zeiss Microscopy.

How do you find defects after bonding?

Buried defects are the hardest problem. IR metrology verifies pad alignment through silicon. 3D X-ray, in CT and laminography modes, measures alignment and overlay errors; high-resolution X-ray imaging has demonstrated 150 nm resolution for sub-micron 3D inspection of the bond interface.

"XRDI tends to be used for fully automated leading-edge wafer processing where the process steps can be more aggressive, and the cost of wafer loss and disruption to the line is more significant," said John Wall, site manager at Bruker JV UK. "We can detect subsurface critical defects on patterned/metalized wafers with zero edge exclusion. Full wafer inspection can be performed at ~20wph."

For cracks and delamination, acoustic micro-imaging with ultrasound near 200 MHz provides the highest resolution. "Ultrasound does not travel through air gaps that have a thickness down to about 0.1 µm," said Bryan Schackmuth, AMI product manager at Nordson Test & Inspection. A 165 MHz transducer resolves 12 µm accurately; a 5 µm void can be detected but not accurately measured, so higher-frequency transducers are in development.

The open challenge: as pitches shrink, metrology must combine optical, interferometric, AFM, X-ray and acoustic methods — each with gaps in resolution, sensitivity, penetration or throughput — and still support high-volume manufacturing.