AI Chips Outpace Test: Insertions Double, Silicon Dies Before Deployment

Test intensity for AI silicon has at least doubled over the AI era, and rack assemblies carrying finished devices are worth $30,000 to $50,000 — sums that no manufacturer can write off because of one defective chiplet. That figure, from Teradyne, frames the core problem now facing the semiconductor industry: chips take longer to design, build and test than the AI workloads they are meant to run stay relevant.

The gap opened with generative AI. It took slightly more than two years from the introduction of ChatGPT in November 2022 to widespread commercial adoption of agentic AI systems — roughly the time required to design, verify and validate a chip, shuttle it through a fab, package it and integrate it into a working system. During those two years, the industry moved from arrays of GPUs for massively parallel multiply-accumulate operations to mixed fleets of GPUs, CPUs and customized programmable accelerators, each demanding different optimization and prioritization schemes.

What changed in test?

Until recently, test targets and insertion timing followed fab processes and the laws of physics, with deterministic, quantifiable results. High-performance data-center processors — and many edge devices — are now multi-die assemblies that take longer to design, manufacture, package and assemble, and their target workloads often change before the chips leave final test.

The test scope itself has widened. Beyond electrical tests, these devices require mechanical integrity analysis, multiphysics simulation, and real-time monitoring of processor and memory utilization, thermal gradients and datapath throughput, plus tracking of accelerated aging effects on signal integrity.

"It's a huge challenge," said Scott Segura, vice president of sales at Advantest. "People are starting to put more active components into the substrate, and moving things closer to each other, so it's turning into more test insertions. What shifts left? What shifts right?"

Segura cited concrete pressure points:

• Functional testing is moving into substrate testing, which previously checked only contact.
• Known good dies must handle 3 kilowatts at the die level, with thermal control during probing.
• Singulated dies are now tested directly.
• Silicon photonics already requires five test insertions.

Where does the data get stuck?

The transition from round wafers to 310 × 310mm panels — adopted to maximize equipment utilization and die count — will require entirely new equipment and processes. Packaging and assembly, once done at one site, is now split between fabs and OSATs, fragmenting data flows.

"Test insertions typically are done at different locations," said Jeorge Hutarte, senior director of product marketing in Teradyne's Semiconductor Test group. Wafer sort and singulated die probe happen at the fab with its own test programs and failure-mechanism data. Interposer substrate test, where a compute die meets a stack of HBM and other chiplets, happens at the OSAT — "a different location with a different test program and a different data collection environment." He added: "In the fabless world, people don't share data unless the customer owns everything."

Jim Schiely, chief of staff for Calibre Semiconductor R&D at Siemens EDA, noted that tool output keeps growing: "Not only are there more tools, but they're all generating more data — and pretty rich modes of data with lots of images." His proposed remedy is AI itself: digital threads of information can be converted into shared models automatically, even across departments with different data models, without waiting years for common formats.

Kimon Michaels, co-founder and executive vice president at PDF Solutions, put the target as networked analytics "across your own supply chain, or collaboration with your partners," with IP protection built in. "We're not there yet as an industry for sure," he said.

What happens when silicon misses the market?

Hyperscalers are pressing EDA vendors to compress design cycles from the current 18 to 24 months toward 6 months — a stated goal of some large chipmakers. Even that would leave a gap against training and inference models that update in hours or days.

"We have customers now that will tape out chips, run their models on them, and they'll end up not going to market with them," said Advantest's Segura. They build derivatives with different memory stacks, core counts or cache sizes. "Even our customers sometimes guess wrong," he said, citing chips that arrived with too little memory, excessive cost, or a shifted use model. Chiplet designs offer one escape: a product planned for 256 cores may ship with 192.

Inaccessible components add another layer. Active parts buried in substrates — dies, inductors, capacitors, voltage regulators — now carry built-in self-test, sometimes borrowed from connected elements. "It's getting more and more complicated, and people are making this up as they go," Segura said.

Cost pressure is pushing screening earlier. Some companies now request a wafer-level burn-in stage between wafer sort and singulated die probing to accelerate infant mortality before die are committed to an interposer stack. "Every wrong screening translates to thousands of dollars of loss because of failures at the data center," Hutarte said. "We cannot throw away $30,000 because of a defective chiplet."

How long can these chips last?

Rework is replacing scrappage, and customers want longer service lives from increasingly expensive hardware. Rahima Mohammed, distinguished engineer and semiconductor technical advisor at Vinci, pointed to workload scheduling as a new trend: moving workloads to limit self-heating and keep devices safe, and reasoning from the nanometer level of transistor self-heating up to package-level power delivery, dielectric degradation and cooling effectiveness.

"In a previous time, PCB packaging was just about adding layers. We just kind of winged it," Mohammed said. "You don't have that option anymore."

Test was historically a small, predictable share of manufacturing cost. It is now a design-specific process, costly and time-consuming, and the use case may have moved again by the time a fully tested chip ships. Until AI settles into a stable pattern of use, chipmakers face hard choices about how much customization competitiveness demands — and how long it will last.