Micron Bets on Wafer Bonding and High-NA EUV for Post-4F2 DRAM

Micron has scrapped 4F2 memory cells from its roadmap, and now the company says wafer bonding plus High-NA EUV lithography will carry its DRAM scaling into the 2030s. The plans, laid out at an event this week, also include two new memory types — vertical HBM and vertical edge inference memory — designed to sit directly on top of processors.

"DRAM is nearing atomic limits at this point," said Scott DeBoer, president and chief technology and products officer at Micron. "Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view."

What does the new roadmap change?

Micron's current 1γ DRAM process is already in high-volume manufacturing. Its successor, 1δ, enters volume production in the second half of 2027 and promises a mid-20% increase in bit density — roughly a quarter more bits per wafer area than today's node. Micron has optimized 1δ for future AI memory products, including HBM5, vHBM, and vEIM.

Beyond that, the picture gets more interesting:

• 1ε (under development): introduces wafer bonding. Micron hasn't disclosed how it will implement the technique or what gains it expects.
• ζÅ (zeta angstrom): Micron's first-generation sub-10nm-class DRAM node, which adopts High-NA EUV lithography.
• ηÅ (eta angstrom): second-generation sub-10nm-class node, adding new materials to keep shrinking cells.

For fabrication technologies spanning the next five to ten years, Micron is collaborating with Albany NanoTech. DeBoer framed the work as fundamental, pre-competitive IP rather than product-ready tooling.

"Albany NanoTech, our announced focus on advanced lithography [is] really driving the High-NA EUV roadmap for DRAM," he said. "In particular at Albany with our team there, focused on the next five to ten years."

3D DRAM also appears on the roadmap, slotted between ζÅ and ηÅ as two generations labeled 3D1 and 3D2. Micron hasn't published architectures or launch schedules, and DeBoer made clear the timing is deliberate.

"In reality, this is a parallel path, and we will implement it in a fashion that is ideal for cost, complexity, and device performance," he said.

Why put memory on top of processors?

The bigger strategic shift is vertical. Micron is developing three new product categories: vertical HBM (vHBM), vertical edge inference memory (vEIM), and custom HBM (cHBM) implementations.

vHBM places memory stacks directly on top of processors — think AI accelerators and AI GPUs — rather than beside them. Shorter connections promise substantially lower latency and higher bandwidth. The trade-off is real, though: stacking memory above a processor creates significant thermal challenges and limits how many stacks fit on an ASIC. Micron expects vHBM to complement conventional HBM, which will keep supplying the bulk of memory capacity in AI accelerators.

vEIM shares architecture and packaging traits with vHBM but targets a different buyer. Where vHBM chases maximum bandwidth for datacenter-class accelerators, vEIM prioritizes energy efficiency for edge AI processors in autonomous vehicles, robotics, and other power-constrained devices. Even so, the first-generation vEIM targets 2 TB/s of bandwidth at under 1 pJ per bit — performance in line with today's HBM4, which runs 8 GT/s over a 2,048-bit interface. Micron plans to tune vHBM, vEIM, and cHBM with customers around their bandwidth, capacity, and power requirements.

Both vertical architectures depend on advanced packaging, particularly hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management is the other hard problem, especially for vHBM. Micron is developing specialized heat-spreading structures that move heat from hot regions of memory base dies through the DRAM stacks.

What's the timeline?

Micron hasn't said when vHBM, vEIM, or cHBM will reach commercial production. The development effort itself signals the direction: future memory performance gains will increasingly come from advanced packaging and tighter integration with processors, forcing DRAM makers and logic developers to work together from the start. For an industry that has treated DRAM as interchangeable silicon, that's the real headline — memory is becoming a critical ingredient of ASIC design rather than a commodity.