CoWoS-L will remain the leading packaging technology for AI chips through 2028, according to a forecast from EE Times Asia.

The projection covers advanced multi-die integration used in accelerators that combine logic and high-bandwidth memory in a single package.

What does the forecast cover?

The five-year horizon through 2028 reflects continued investment in manufacturing capacity, design tooling, and customer adoption already centered on CoWoS-L.

EE Times Asia frames this period as one of structural continuity rather than disruption at the technology layer. The packaging approach sits at the center of supply chains that chip designers, substrate makers, and OSAT partners have built over multiple production cycles.

Design wins at major AI accelerator programs lock in tooling, IP, and qualification investment for years at a time. Switching costs across substrate suppliers and EDA flows make displacement within a half-decade window difficult.

How does CoWoS-L differ from earlier variants?

CoWoS-L extends earlier CoWoS generations by replacing a full silicon interposer with an RDL-based interposer that uses local silicon bridges. The "L" designation refers to this local-bridge architecture, which lets the package span beyond a single reticle exposure.

The approach maintains signal integrity across the multi-die layouts that pair large logic dies with stacks of high-bandwidth memory. Earlier CoWoS variants — including CoWoS-S with a complete silicon interposer — addressed smaller package footprints and lower die counts.

As AI accelerators grew in transistor budget and memory capacity, CoWoS-L's scalability moved it to the front of the field. The variant now anchors the highest-volume advanced packaging lines in the industry.

Why does packaging now constrain AI output?

AI accelerator performance depends on memory bandwidth and inter-die interconnect density alongside raw transistor counts. CoWoS-L supports package-level integration of high-bandwidth memory stacks adjacent to compute dies, a layout that defines current-generation training and inference chips.

Capacity for advanced packaging of this class has, at times, determined AI chip shipment volumes more than wafer output alone. Production lines running CoWoS-L operate with long qualification cycles, multi-month lead times, and tightly matched substrate supply.

Order books at the major foundries running CoWoS-L have run ahead of capacity for extended stretches during the current AI build-out. Customers without allocation have waited quarters for slots.

What about competition after 2028?

Other advanced packaging approaches — including competing interposer, bridge, and 3D-stacking schemes — target overlapping use cases. The forecast assumes none will displace CoWoS-L as the lead technology for AI accelerators within the window.

A shift could come from successor CoWoS variants, alternative foundry processes, or a move toward fully 3D-stacked architectures that reduce or replace interposer-based integration. The five-year horizon gives planners a defined timeframe to amortize tooling and qualification costs.

What are the supply-chain implications?

For chip designers, system integrators, and equipment suppliers, the projection supports continued investment in the CoWoS-L ecosystem. Substrate suppliers, OSAT partners, and EDA tool vendors built around this packaging technology can plan on demand continuity through 2028.

The forecast also clarifies risk: any delay in capacity expansion, substrate yield, or bridge silicon supply translates directly into AI chip shipment slippage. Buyers structuring 2025–2028 product roadmaps now have a stable central reference point.