GlobalFoundries will manufacture silicon interposers for TSMC, the New York-headquartered foundry confirmed, extending its role in 2.5D advanced packaging and adding an external line to a process TSMC has historically kept in-house.

The arrangement makes GlobalFoundries the first third-party silicon interposer supplier producing for TSMC at commercial scale. TSMC has run interposers on its Hsinchu and Taichung lines since commercialising its chip-on-Wafer-on-Substrate (CoWoS) process in 2011.

What does the deal cover?

Silicon interposers are 100 µm to 200 µm thick silicon slices, produced on 200 mm or 300 mm wafers. They carry through-silicon vias (TSVs) and fine-pitch redistribution layers that route signals between logic, memory and I/O chiplets mounted on top. Die-to-die pitch sits below 10 µm.

GlobalFoundries did not disclose volumes, wafer sizes or product mix. The announcement does not name a CoWoS variant — CoWoS-S, CoWoS-R or CoWoS-L — nor does it specify whether the interposers will feed only TSMC's own packaging lines.

Why is the deal notable?

TSMC has treated interposer processing as a competitive asset, integrating it with its front-end fabs and bumping facilities. The decision to outsource any slice of that chain to a leading-edge foundry rival signals either capacity pressure or a deliberate diversification of supply.

GlobalFoundries competes with TSMC in trailing-edge and mainstream nodes — the company exited the 7 nm race in 2018 — but the two firms do not overlap in advanced logic. A packaging partnership avoids cannibalisation while using GlobalFoundries' 300 mm capacity at Essex Junction, Vermont.

TrendForce projected in late 2024 that the global advanced packaging market will reach USD 79.4 billion in 2025, up from USD 38.2 billion in 2023, with 2.5D and 3D formats driving the largest share of growth.

What does GlobalFoundries bring?

GlobalFoundries operates a 12-inch line at Essex Junction, Vermont, inherited from IBM's microelectronics business. The site produces silicon germanium and RF SOI wafers and has been qualified for FD-SOI and BCD processes.

The company has worked on interposer technology since at least 2020, when it announced a silicon photonics platform with silicon interposer integration. Its 45RFE and 22FDX PDKs support TSV designs, though qualification for high-volume CoWoS-compatible interposers had not been announced previously.

The equipment list overlaps with foundry back-end-of-line tools: TSV etch, CVD barrier/seed, copper damascene plating, fine-pitch RDL lithography.

What remains unanswered?

• Wafer volumes per month and how they scale across 2025 and 2026.
• Whether the interposers feed TSMC's CoWoS lines exclusively or go to external customers.
• The process node of the interposer itself: older 65 nm or 45 nm flows versus advanced 5 nm-class redistribution wiring.
• Contract structure — pure foundry, joint qualification, or licensing of TSMC's interposer process.

Yole Group estimated in Q1 2025 that CoWoS capacity must reach roughly 75,000 wafers per month by end-2026 to meet AI accelerator demand, against a 2024 base below 35,000 wpm. Any incremental supply from Vermont will be measured against that gap.

Without disclosed volumes, the lead-time impact stays unclear. CoWoS allocation has been the binding constraint on AMD Instinct, Nvidia Blackwell and other AI accelerator shipments through 2024 and into 2025, and the industry will track GlobalFoundries' interposer output quarter by quarter.