TSMC will double its CoWoS advanced packaging capacity by 2028, according to a Wccftech report, as the AI accelerator shortage that has throttled high-end GPU shipments spills over to rival foundries.

The expansion targets TSMC's Chip-on-Wafer-on-Substrate (CoWoS) platform, a 2.5D packaging process that places logic and high-bandwidth memory dies on a silicon interposer. CoWoS has become a critical chokepoint for AI accelerator production: NVIDIA's H100, H200, and B100 GPUs, AMD's MI300 and MI325 accelerators, and Broadcom's custom AI silicon all depend on the technology.

What is CoWoS and why is it constrained?

CoWoS integrates multiple chips on a single substrate using through-silicon-via interconnects. TSMC introduced the technology in the early 2010s and has since added four variants: CoWoS-S with a silicon interposer, the RDL-based CoWoS-R, the large-format CoWoS-L introduced in 2024, and the 3D-stacking SoIC family.

Three factors drive the current bottleneck. Hyperscaler demand for large-language-model training clusters has surged. Available interposer supply is limited because advanced packages now measure up to roughly 120 by 150 millimeters in their largest configurations, requiring specialized wafer-handling tools that few facilities can run. Yield ramp-up times for new package types typically exceed twelve months.

How is the shortage affecting TSMC's customers?

TSMC has allocated CoWoS output by customer priority, with NVIDIA historically receiving the largest share. AMD, MediaTek, and Broadcom have reported reduced allocations in certain quarters, pushing workloads toward alternative suppliers.

AMD confirmed in 2024 that it had qualified Samsung's 4nm logic and packaging for certain products, partly to reduce single-source exposure on CoWoS. Intel's foundry services have courted AI accelerator customers with EMIB and Foveros packaging, though volumes remain far below TSMC's CoWoS output.

When will supply catch up?

The doubling timeline referenced in the Wccftech report covers a four-year window. TSMC has guided that CoWoS capacity expanded significantly in 2024 and 2025, with further lines coming online through 2026 and 2027 across its Tainan, Taichung, and Arizona sites. A second doubling by 2028 would compound that growth on top of the existing baseline.

TSMC executives have repeatedly stated that advanced packaging, not leading-edge wafer production, has been the binding constraint on AI chip deliveries. The company has committed multi-billion-dollar capital expenditure to packaging facilities, including dedicated CoWoS and SoIC lines.

What does the spillover to rivals mean?

Customers diversifying away from TSMC's CoWoS face tradeoffs. Samsung's 4nm and 3nm packaging capacity remains limited, and its I-Cube technology has won only a small share of external AI customers. Intel Foundry's advanced packaging unit has signed deals with hyperscalers, including Microsoft for custom Maia silicon, but volume production remains in early stages.

For TSMC, losing packaging share to competitors is both a near-term revenue hit and a strategic signal that no single foundry can indefinitely dominate the leading edge. Hitting the 2028 doubling target, if executed on schedule, would close the immediate supply gap and restore pricing leverage.

What could derail the plan?

The 2028 timeline assumes continued AI accelerator demand growth. A slowdown in hyperscaler capital expenditure, a shift toward smaller model architectures requiring less HBM, or adoption of alternative interconnect technologies such as optical co-packaging could alter the trajectory. For now, CoWoS remains the binding constraint on AI chip shipments, and TSMC's execution will determine whether the industry rebalances before competitors close the gap.