SK Hynix has laid out the advanced packaging technologies it plans to use for its next-generation HBM memory, and Intel's EMIB is part of the package. The disclosure, reported by Wccftech, signals how the Korean memory maker intends to keep pushing bandwidth density as conventional scaling paths narrow.

For SK Hynix, packaging is no longer an afterthought in the HBM roadmap. It is becoming the primary lever for raising capacity and performance per stack, and the company is now speaking publicly about the specific interconnect and bonding methods it intends to deploy.

What is Intel EMIB doing in SK Hynix's HBM plans?

EMIB — Intel's Embedded Multi-die Interconnect Bridge — is a silicon bridge embedded in the package substrate that connects dies with a dense, short interconnect path. The technology avoids a full silicon interposer while still delivering die-to-die bandwidth that traditional substrate routing cannot match.

Intel developed EMIB for its own multi-chip products, and licensing or adopting it for HBM production would place SK Hynix's memory stacks on packaging infrastructure that originated outside the memory industry. The move fits a broader pattern: as HBM stacks grow taller and wider, memory makers are borrowing logic-industry packaging tools to keep signal integrity and thermals under control.

Why is packaging now the bottleneck for HBM?

Each HBM generation adds more DRAM dies per stack and runs the interface faster, which puts pressure on two things: the wiring that moves data between dies, and the heat that accumulates inside a tall stack. Advanced packaging addresses both.

Better die-to-die interconnects raise the aggregate bandwidth available to accelerators that depend on HBM. Thinner bonding layers and improved thermal paths let designers stack more dies without hitting power limits. SK Hynix's decision to unpack its packaging roadmap publicly reflects how central these choices have become to competitiveness in the AI memory market.

The company's current stacks already rely on through-silicon vias to connect dies vertically. EMIB and similar bridge technologies complement that approach by improving the horizontal links between dies and the logic base die beneath them.

What comes after stacked dies?

SK Hynix is also looking toward 3D structures for future HBM generations, according to the report. Rather than continuing to add planar dies one on top of another, 3D structures would build memory cells and interconnects in genuinely three-dimensional arrangements.

That shift matters because the height of a conventional stack is bounded by thermals and by the mechanical limits of thin-die handling. A move to 3D structures would push beyond those limits, but it also demands new manufacturing steps, new bonding techniques and new ways of moving heat out of the stack. SK Hynix framing 3D as a future direction indicates the company sees the current die-stacking formula running out of headroom over the longer term.

What does this mean for the AI memory market?

HBM demand from AI accelerator makers has turned packaging capability into a competitive differentiator among the three major suppliers — SK Hynix, Samsung and Micron. Customers buying accelerators care about delivered memory bandwidth, and delivered bandwidth depends on packaging as much as on the DRAM process node itself.

By publicly detailing its packaging direction, SK Hynix is positioning its next-generation HBM as a platform built on interconnect engineering, not just denser DRAM. The inclusion of Intel EMIB in that picture also points to growing cross-licensing of packaging technology across the industry, as memory and logic manufacturers converge on similar multi-die integration problems.

The timeline for the 3D structures remains open. What is clear from the disclosure is the direction: near-term HBM generations lean on bridge interconnects such as EMIB, while the long-term roadmap moves the memory stack into three dimensions.