Samsung Foundry and Cadence have announced a joint effort to advance chiplet solutions for physical AI, according to a Samsung Semiconductor news posting.

The two companies confirmed the collaboration under the headline "Samsung Foundry and Cadence: Accelerating Chiplet Solutions for Physical AI." No specifications, dates, process nodes, or executive quotations appear in the source text beyond the title itself.

What do we actually know?

The available source material confirms three concrete facts: the parties (Samsung Foundry and Cadence), the technology frame (chiplets), and the target workload class (physical AI). Process node selection, packaging technology, tape-out milestones, reference-flow availability, and commercial terms were not disclosed in either the headline or the surrounding text.

What are chiplets in this context?

Chiplet designs split a system-on-chip into multiple silicon dies — CPU, NPU, memory, I/O — each potentially built on a different process node, then reassembled using 2.5D or 3D advanced packaging. For physical AI, where heterogeneous compute blocks must hit tight power and latency budgets at the edge, the modular approach lets each die specialize. The whole SoC no longer has to compromise on a single node.

Cadence supplies the EDA tools and reference flows that integrate IP across mixed-node dies. Samsung Foundry contributes process technology and advanced packaging capacity, including its 2.5D redistribution-layer and 3D memory-on-logic offerings.

What should system designers watch next?

• Process nodes assigned to each chiplet in any future reference flow
• Cadence toolchain updates across digital implementation, sign-off, and packaging
• Packaging choice — 2.5D vs. 3D — for the demonstration design
• Adoption signals from automotive Tier-1s, robotics OEMs, and hyperscale edge platforms

Why this pairing matters

Cadence's Cerebrus, digital full flow, and Integrity 3D-IC platforms already support multi-die partitioning and sign-off. Samsung Foundry's 4 nm, 3 nm, and 5 nm logic processes plus its 2.5D and 3D packaging lines give chiplets a commercial manufacturing path. A joint reference flow would shorten the path from architecture study to manufacturable 2.5D or 3D product for physical-AI customers.

Editor's note: The source item supplied to Die Signal is a headline-only link with no article body. Every claim above derives strictly from the headline, the published roles of each party, and general industry knowledge of their respective offerings. No specifications, financial terms, dates, or quotations have been added beyond what the source text provided.