The first standardized specification for High Bandwidth Flash (HBF) appeared at FMS 2026, jointly produced by SK hynix and Sandisk. The two memory companies framed the document as the foundation for a new class of AI memory subsystems targeting capacity-bound AI workloads.

HBF describes a stack architecture pairing high-capacity NAND dies with a wide-I/O logic die, applying the bandwidth-oriented design pattern that took HBM from niche component to essential element inside AI accelerators. The target workloads are those where capacity, not peak bandwidth, constrains the system. They include long-context LLM inference, retrieval-augmented databases, and inference-time KV caches that overflow DRAM.

What does the HBF standard actually specify?

The specification covers pinout, thermal envelope, and signaling for stacked NAND-plus-logic modules. It does not pin a single NAND cell type; QLC and TLC are both candidates, leaving vendors room to differentiate on cost per terabit. The wide-I/O logic die takes over the controller role, offloading wear-leveling and translation from the host accelerator.

The architecture mirrors the path HBM took: a published spec for a stacked memory hierarchy, with capacity scaling through die-stacking rather than process shrinks. Vendors that already ship HBM-class packaging now have a NAND counterpart to qualify.

Why does the industry need an HBF standard?

Until this release, NAND-plus-logic integration for AI ran on proprietary controller-to-die bridges. Each accelerator vendor qualified a different flash variant, slowing adoption and capping volume. A published specification gives packaging houses, controller-IP suppliers, and hyperscaler buyers one common reference design to build against.

SK hynix and Sandisk jointly published the document, an unusual cross-vendor memory standards effort. The two companies sit on opposite ends of the NAND industry. Sandisk sells across consumer and enterprise channels with a broad controller portfolio. SK hynix supplies the high-bandwidth packaging expertise gained shipping HBM3 and HBM3E to leading AI accelerator customers.

What will FMS 2026 actually show?

FMS—formerly the Flash Memory Summit—runs annually in Santa Clara, California. The 2026 edition is the public debut for HBF reference designs, joint technical sessions from SK hynix and Sandisk, and the first public look at the specification's pinout, signaling, and module-level thermal envelope.

The partners will present AI memory solutions built on the new spec. Booth demonstrations are expected to include reference modules and interoperability test hardware, though neither company has confirmed a sampling timeline.

What does the spec leave unanswered?

• Maximum stack height or capacity per package
• Per-pin bandwidth target
• Power envelope per module
• Pricing or volume schedule
• List of AI accelerator design partners

These details typically emerge in the months following an initial spec release, either at follow-up conferences or through formal standards body submissions.

How does HBF change AI memory economics?

Capacity-bound AI workloads pay a premium today. DRAM-only LLM serving scales linearly with parameter count and context length, pushing memory cost ahead of accelerator silicon cost. NAND costs roughly an order of magnitude less per bit than DRAM, and HBF attempts to retain enough bandwidth to feed modern accelerators without going through PCIe.

If SK hynix and Sandisk hold the published specification, the next 12-18 months will see controller IP, packaging, and qualification work converge around a common design. Hyperscalers can then plan capacity ramps without depending on a single supplier.

What questions should buyers bring to FMS 2026?

• Will Samsung publish a competing HBF profile, or align with the SK hynix/Sandisk document?
• Which AI accelerator vendors have pre-validated against the spec?
• When does the first HBF-equipped product reach sampling?
• What per-package capacity floor does the first generation target?
• Is there a formal JEDEC submission path, and what is its timeline?

The August conference in Santa Clara will set the tone for the next phase of AI memory competition. Follow-up technical disclosures—likely at the keynote and partner sessions—will determine whether HBF scales into production or remains a reference design.