Siemens and TSMC have introduced an AI agent that automates the correction of design rule violations in chip development, according to a report by CRN Asia. The tool targets a bottleneck that has resisted automation for decades: the process of finding and fixing errors that occur when a layout violates the geometric and manufacturing constraints defined in a foundry's design rule manual.

Design rule checking, or DRC, sits at the core of physical verification. Every chip layout that a customer intends to fabricate at TSMC must pass a comprehensive set of rules before tape-out. These rules govern minimum feature widths, spacing between structures, enclosure requirements, and hundreds of other geometric constraints at advanced process nodes. When the checker flags a violation, an engineer normally has to identify the cause, decide on a correction, apply the fix, and re-run verification. At leading-edge nodes, a single design can generate thousands of such violations, and each manual fix consumes engineering time while risking the introduction of new errors elsewhere in the layout.

The new AI agent from Siemens and TSMC aims to take that corrective loop out of human hands. Rather than simply reporting violations, the agent is designed to propose and apply fixes automatically, then verify that the corrections satisfy the applicable rules. This marks a shift from detection — a solved problem since the earliest days of electronic design automation — to remediation, which has remained stubbornly dependent on engineering judgment.

The collaboration pairs two companies with complementary positions in the semiconductor supply chain. TSMC, the world's largest contract chipmaker, defines the design rules that reflect the capabilities and constraints of its manufacturing processes. Siemens, through its EDA business, supplies the physical verification and design implementation tools that engineers use to build and check layouts against those rules. An AI agent that connects the two sides — the rule definition and the rule enforcement — requires cooperation between foundry and tool vendor at a level that goes beyond traditional tool licensing.

For chip designers, the practical appeal is throughput. Fixing DRC violations typically occurs late in the design cycle, under schedule pressure, and close to tape-out deadlines. Any reduction in the manual effort required at this stage translates directly into faster iteration and earlier delivery of manufacturable layouts. The automation also reduces the risk of human error at a stage where a single bad fix can cascade into new violations across a dense layout.

The introduction of an AI agent into this workflow also signals a broader direction for EDA software. Major tool vendors have moved aggressively to embed machine-learning capabilities across the design flow, from placement and routing optimization to lithography-aware analysis. Physical verification has historically been among the least automated segments of the flow precisely because rule interpretation and fix strategies vary so widely by context. An agent-based approach, where the system reasons about a specific violation and its surroundings rather than applying a fixed recipe, addresses that variability in a way earlier automation attempts did not.

CRN Asia's report did not specify which Siemens product line carries the agent, which TSMC process nodes it supports, or whether the tool is already available to customers in general release. Details on availability, licensing terms, and measured productivity gains have not been disclosed in the initial announcement.

The companies have framed the agent as part of an ongoing collaboration rather than a one-off tool release. As process geometries shrink and design rule sets grow more complex at each node, the volume and subtlety of violations that engineers must resolve continues to increase. Automation of the fix cycle, if it performs as intended, removes one of the last labor-intensive steps between a completed layout and a clean, manufacturable design — and gives both companies a concrete answer to the question of where AI delivers measurable value in chip design rather than speculative promise.