TSMC used its Open Innovation Platform (OIP) Forum to convert agentic chip design demonstrations into production-ready design flows, The Futurum Group reports.

The Hsinchu-based foundry runs the annual OIP Forum to align EDA vendors, IP suppliers, design services partners and internal methodology teams around a common process-design kit (PDK) and reference flow. Reporting on this iteration centers on agentic chip design — the application of autonomous AI agents to portions of the specification, architectural exploration, RTL generation and verification work in chip projects.

TSMC's reference flows set the working baseline for most commercial silicon designed at advanced nodes, including the bulk of mobile, AI accelerator and data-center SoCs. A formal reclassification from research demo to qualified customer flow typically means sign-off correlation, model coverage and methodology documentation have cleared foundry review.

TSMC framed the work as a move beyond demo reels. Demonstrations staged previously as research previews are now packaged as flows customers can drop into ongoing tape-out projects, with EDA partner vendors exposed through standard PDK integration points.

What does "agentic" mean in this context?

Agentic design refers to AI systems that take sequences of actions toward a goal with limited human supervision, rather than single-shot completions from a generative model. In chip work this maps to tools that iterate on synthesis constraints, run testbenches, fix lint and timing violations, and re-floorplan blocks without an engineer stepping through each step manually.

Applied to advanced-node design, the approach targets one of the costliest bottlenecks in the industry: engineering-hour spend per mask layer at 5nm, 3nm and below. If an agent can close a meaningful share of those loop iterations, the implied savings affect both NRE budgets and time-to-tape-out.

What does moving from demo to production actually require?

A production-ready EDA flow at a TSMC-class foundry requires three layers:

• PDK alignment — models, design rules and tech files matched to the current silicon revision
• Qualified tool versions from EDA vendors with sign-off correlation against silicon
• Documented methodology so design teams at customer companies can run the flow without inventing steps

A demo crossing into production has to satisfy all three. Forum presentations typically showcase flows that already meet the bar; demos that fail sign-off correlation remain on the research track.

How does agentic flow reshape EDA and IP economics?

The classification reflects a shift in how EDA stacks are organized. Traditional point tools — synthesis, place-and-route, timing analysis, sign-off — were built around engineer-in-the-loop operation. Agentic systems invert the stack: the engineer defines constraints and reviews outputs, while the agent drives the iteration loop between them.

Agentic flows shift where the productivity gain shows up. Traditional EDA tool revenue scales with seats and tool runs; agentic systems amortize one design iteration across many smaller ones, reducing per-iteration license consumption. Vendors that own the agent orchestration layer stand to capture recurring revenue tied to chip programs rather than per-tool-call licensing.

IP suppliers see a parallel change. As agents compose subsystems from pre-qualified IP blocks, the IP catalog itself becomes part of the design surface the agent searches, putting catalog depth and metadata quality at a premium.

What remains unclear

The Futurum Group report does not specify which EDA partner flows have already crossed from demo to production at the OIP Forum, nor provide customer tape-out timelines. The headline framing — "demos into production flows" — is consistent with a phased rollout: research-track agents that complete formal sign-off over the next product cycle, alongside flows already shipping today for less critical IP integration work.