Siemens and TSMC have extended their EDA partnership with an AI agent that identifies and fixes design rule violations across digital and custom chip designs, combining Siemens' Calibre, Aprisa and Solido software into one workflow intended to cut manual signoff work before tapeout.

The integrated system targets a bottleneck that consumes engineering time at every process node: checking whether a chip layout complies with the manufacturing rules of a given process before the design is finalized. The initiative also covers AI-assisted chip implementation alongside TSMC's advanced manufacturing processes, 3D packaging architectures and silicon photonics.

What does the AI agent actually do?

The automated workflow forms part of Siemens' Fuse EDA AI System and Fuse EDA AI Agent, which are engineered to carry out longer, multi-step electronic design automation tasks. Siemens states the system can:

• coordinate actions across several design tools;
• assess intermediate results;
• verify its work as a task progresses.

To handle these longer-running workloads, the architecture incorporates NVIDIA AI technologies to improve token efficiency, reasoning and execution. In design rule checking, Calibre, Aprisa AI and Solido Fuse work in close coordination to identify, analyse and resolve violations. Calibre Check Assist supplies contextual guidance and design rule details when engineers investigate problems.

Siemens and TSMC are applying similar agent-based capabilities to custom chip design and physical implementation, where Aprisa supports automated placement and routing — determining how components are arranged on a chip and how their connections are laid out.

"AI presents a significant opportunity to drive productivity and efficiency across increasingly complex semiconductor design workflows," said Aveek Sarkar, director of the ecosystem and alliance management division at TSMC. "Our collaboration with OIP partners like Siemens focuses on delivering intelligent, trusted automation that empowers engineers to navigate rising design complexity while achieving stringent performance and energy-efficiency targets."

Sarkar added: "By integrating AI into critical stages of the design process, we enable mutual customers to leverage TSMC's industry-leading processes and advanced packaging technologies to accelerate the expansion of AI innovation."

The deployment concentrates AI automation on defined engineering tasks where the software can check results during execution. In practice, this addresses repetitive design-rule debugging and implementation work that would otherwise require far more manual intervention.

How far does the work extend into 3D design?

Siemens and TSMC are expanding support for TSMC 3DFabric technologies, which combine multiple dies and packaging technologies within more complex semiconductor designs. Calibre 3DStack Advanced now supports processing across multiple machines for inter-chiplet antenna verification, including designs using TSMC-SoIC wafer-level 3D stacking. Certification work is under way for TSMC's CoWoS-L packaging technology.

The joint efforts cover:

• thermal analysis;
• chip-package co-design;
• routing between separate dies.

Calibre 3DThermal has been certified for static and transient thermal analysis of TSMC 3DFabric technologies and the TSMC A16 process, and enablement is complete for a system-on-wafer thermal reference flow.

The companies are also progressing support for 3Dblox, TSMC's framework for 3D chip design, including chip-package co-design workflows. Within this environment, Aprisa is being developed to automatically determine die-to-die routing configurations based on simulation results and signal-integrity requirements.

Silicon photonics forms another dimension of the collaboration through TSMC-COUPE, the Compact Universal Photonic Engine. Siemens tools are already enabled for design, implementation and verification work with the technology; further thermal validation remains in progress.

Which tools gained new TSMC certifications?

Siemens has secured certifications for several verification tools on TSMC's A14 process:

• Calibre nmDRC — design rule checking;
• Calibre nmLVS — comparing a physical chip layout with its circuit design;
• Calibre xACT — extracting electrical characteristics;
• Calibre PERC — electrical reliability checks.

The Solido Simulation Suite is certified for SPICE accuracy across TSMC N3C, A16 and A14 technologies, covering analogue, radio-frequency and memory verification.

For power integrity, Siemens' mPower software is certified for transistor-level voltage-drop and electromigration analysis on TSMC N2P for digital and analogue designs, and on N3C for analogue designs. Both companies continue work on N2 and N3 reference flows, while certification of Aprisa and mPower analogue software for A14 remains under way.

Siemens has also opened its Xcelerator Academy training programme to TSMC Design Center Alliance partners alongside mutual customers. The offering includes a digital implementation tutorial based on TSMC's 5 nm process technology.