Synopsys and TSMC have broadened their design tool and IP support for AI system-on-chip development, according to a joint announcement covered by engineering.com.

The expansion targets the demand for AI accelerators and AI-integrated SoCs. Synopsys supplies electronic design automation (EDA) software and pre-verified IP blocks that chip designers integrate into their layouts. TSMC manufactures the resulting silicon at scale. Tight EDA-foundry alignment reduces the cost of moving a design from concept to fabricated wafer.

What does the announcement cover?

The joint work spans two areas: design enablement and IP availability. Design enablement includes updated process design kits (PDKs), reference flows, and sign-off decks that let EDA tools target a specific manufacturing process. IP availability adds pre-built functional blocks — memory compilers, SerDes, foundation IP, and AI-oriented accelerators and interconnects — that customers drop into their chip designs.

For AI workloads, the timing matters. Demand for inference and training silicon has pushed tape-out schedules toward advanced process nodes, where any mismatch between IP behavior and foundry process rules produces respins that cost millions of dollars and slip delivery dates by quarters.

Why AI silicon specifically?

AI systems require heterogeneous compute layouts — CPUs paired with neural processing units and high-bandwidth memory interfaces — assembled largely from licensed IP rather than built from scratch. Pre-qualified IP at the right node cuts design cycle time and verification overhead. Both companies treat AI silicon as a structural part of the semiconductor market through the rest of the decade.

Who are the partners?

Synopsys, headquartered in Sunnyvale, California, supplies EDA tools used by the majority of commercial chip companies. Its portfolio spans digital implementation, analog/mixed-signal design, verification, and IP.

TSMC, based in Hsinchu, Taiwan, manufactures chips for a customer list that includes Apple, Nvidia, AMD, and Qualcomm. Its process roadmap anchors advanced-node silicon release cadence worldwide.

The two companies maintain a long-running collaboration through TSMC's Open Innovation Platform and the Synopsys TSMC Reference Flow program.

Market read

The announcement extends a pattern of pre-nodal collaboration between EDA vendors and foundries. Cadence, Synopsys' primary EDA competitor, runs a parallel program with TSMC and other foundries. Siemens EDA maintains an active IP catalog as well. Competitive pressure is to ship silicon-proven IP at the same node as the foundry's risk-production milestone, not one or two nodes behind.

For chip companies targeting AI workloads, the practical effect is shorter time-to-tape-out at advanced nodes. For Synopsys, the deal extends its IP and tool footprint into the highest per-design revenue segment of the market. For TSMC, alignment with the leading EDA vendor reduces friction for customers choosing the foundry for AI silicon.

What stays undisclosed

The source coverage did not specify which IP products, process nodes, release dates, or financial terms apply. engineering.com carried only the headline without a full release text.