AMD's EPYC 9006 Venice Launches With 256 Cores and a 5.3GHz Surprise

AMD's new EPYC 9006 "Venice" flagship packs 256 cores and 512 threads per socket — a 33% jump over EPYC 9005 "Turin" just one generation ago — and it ships on an entirely new SP7 platform. The launch, unveiled in full today, marks the debut of the Zen 6 architecture, which will drive AMD's server and client roadmaps for the next two years.

For buyers, the headline numbers stack up fast. Venice moves core manufacturing from 4nm/3nm on Turin down to TSMC's N2 node — the foundry's first GAAFET-based process. Peak power rises from 500W to 600W, and memory support jumps from 12 channels of DDR5-6400 to 16 channels of DDR5-8000 or MRDIMM-12800, with capacity climbing from 6TB to 8TB. I/O shifts from PCIe 5.0 x128 to PCIe Gen6 x96 in single-socket configs. AMD also doubled the core complex: 32 cores plus 128MB of cache, versus 16 cores plus 32MB on both prior generations.

What does the spec bump change for buyers?

Just before launch, AMD revised one SKU upward. The high-frequency EPYC 9686F was originally announced at a 5.0GHz peak boost; the shipping silicon now clocks at 5.3GHz. AMD says final Zen 6 CCD silicon turned out better than expected, so the early SKU stack was conservative. That means the fastest Venice now outruns the fastest Turin after all.

The rest of the stack holds:

• EPYC 9996 — 256 cores, 4.1GHz boost, 1,024MB L3, 600W
• EPYC 9966 — 192 cores, 4.0GHz boost, 768MB L3, 600W
• EPYC 9846 — 168 cores, 3.7GHz boost, 768MB L3, 500W
• EPYC 9756 — 128 cores, 4.0GHz boost, 512MB L3, 500W
• EPYC 9G76 / 9656 — 96 cores each, 4.8GHz and 3.7GHz boost respectively
• EPYC 9686F — 96 cores, 5.3GHz boost, 384MB L3, 500W
• EPYC 9556 / 9586F — 64 cores, 300W and 500W

Note the asymmetry: only the 9686F gets the frequency bump. The 64-core 9586F, also rated at 5.3GHz, keeps its original spec. If you want AMD's highest-clocked Venice, you buy the 96-core part.

Why is AMD splitting the lineup?

Venice breaks the EPYC family across two sockets. The high-end SP7 platform launches today, and a more restrained SP8 platform follows early next year. AMD is also segmenting by workload: the -X high-cache parts return with Venice-X, and a LPDDR5X-based Verano variant is in the pipeline. The series covers everything from rank-and-file servers to HPC systems and AI nodes — AMD calls it the most ambitious EPYC innovation since the I/O die arrived with EPYC 7002.

Architecturally, AMD is leaning on chiplets harder than ever, using advanced packaging to tie them together. That's what lets the company exploit N2 fully: more transistors per Zen 6 core for a claimed 20% IPC uplift plus higher clocks, and more cores per package than before.

How does this fit the AI demand picture?

The launch lands amid what AMD describes as unprecedented demand for server CPUs powering AI host nodes and agentic workloads. Beyond raw throughput, AMD points to PCIe Gen6, new virtualization and security features, and a recent acquisition of a software engineering firm to develop software replacing DRAM with flash memory.

The market stakes are concrete. AMD already holds 46% of x86 server CPU revenue share, and the company expects Venice to push it above 50% for the first time. Its data center division projects revenues surpassing Intel's in Q4 of this year, based on last week's earnings. AMD expects to capture server CPU market leadership within the next 12 months.

First benchmarks are in. The flagship EPYC 9996 has already gone through the AgentSTH V7 agentic-workload suite, alongside preview components of the 2027 AgentSTH V8 — a benchmark project built by profiling workloads across dozens of platforms going back roughly a decade of server architectures.