AMD EPYC 9006 Venice Ships: 256 Cores, 512 Threads, PCIe Gen6

AMD's sixth-generation EPYC server processor, codenamed Venice, tops out at 256 cores and 512 threads per socket, and the company says the silicon is in production today. The EPYC 9006 family uses Zen 6 and Zen 6c cores and adds PCIe Gen6 (the interconnect linking the CPU to GPUs, network cards and NVMe drives). The announcement, covered by The FPS Review and ServeTheHome, turns a roadmap name into shipping hardware.

What did AMD actually confirm?

The flagship model is the EPYC 9996. In AMD's own SPECrate 2026 Integer testing, the company reported 1.2x per-core performance and 2.24x platform-level performance against an Nvidia Vera-based platform. Those are vendor numbers. AMD ran the tests, picked the comparison system and published the result; no independent matched comparison exists in the reviewed materials.

The confirmed record is narrow but concrete:

• Product family: AMD EPYC 9006 Series, sixth-generation EPYC.
• Cores: Zen 6 and Zen 6c, up to 256 cores and 512 threads.
• I/O: PCIe Gen6.
• Flagship: EPYC 9996.
• Embedded variant: EPYC Embedded 9006 SP7, up to 256 cores, PCIe Gen 6 plus CXL 3.1 (a protocol that attaches extra memory or accelerators over the same physical lanes).
• Manufacturing: TSMC 2nm, ramping in Taiwan, announced May 21, 2026.

Clock speeds, cache sizes, wattage and pricing do not appear in the official materials. Secondary reports cite them; AMD's excerpts do not confirm them.

How should the benchmark claims be read?

The two ratios measure different things. Per-core performance measures one core. Platform-level performance measures whole-system throughput, which depends heavily on core count. A 2.24x platform gap against only 1.2x per core says most of the lead comes from having far more cores, not from each core being dramatically faster.

CEO Lisa Su put the generational claim in her own words at the Advancing AI 2026 keynote: "Venice starts with our all-new Zen 6 core." She added: "We have higher IPC, higher frequency, and that delivers up to 1.8x more performance than Turin." That figure compares Venice to AMD's own prior generation. It says nothing about Intel Xeon, and AMD supplied no Xeon figures at all.

Madhu Rangarajan, AMD's corporate vice president for compute and enterprise AI, told media, as reported by TechPowerUp: "We think that the EPYC 9006 CPU is the best CPU for the agentic era, and spoiler alert, we didn't magically know four years ago that agentic was going to be a thing and purpose-built something for agentic." Every one of these statements is vendor marketing. They show positioning, not proof.

Does the manufacturing detail matter?

On May 21, 2026, AMD announced Venice was ramping on TSMC's 2nm process in Taiwan, with future plans for TSMC's Arizona facility. The Arizona mention signals US-based capacity is in AMD's stated plans; the company gave no date or volume, so treat it as direction, not a schedule. Leading-edge wafers are scarce, and every 2nm design competes for the same supply. AMD has published no unit forecasts.

The public timeline runs in order: Su introduced Venice at CES 2026, AMD confirmed the 2nm ramp on May 21, the Advancing AI keynote carried the 1.8x claim, and November 2026 launch coverage declared production.

What about the embedded line and the buyers?

The EPYC Embedded 9006 SP7 carries the same 256-core ceiling plus CXL 3.1, aimed at network appliances, storage arrays and industrial controllers. GIGABYTE already lists EPYC 9006 platforms. AMD supplied no SKU lists, availability dates or pricing for the embedded parts.

For buyers, the unknowns are long: no official price, no single general launch date, no model-by-model specs, and no independent SPECrate 2026 results against Vera. More cores also carry risks. Per-core licensed software could make a 256-core chip expensive, and memory bandwidth decides whether 512 threads deliver at all.

The verdict: Venice is real, in production, and aimed at both Intel and Nvidia. The evidence is lopsided. Buyers should run their own workloads against Xeon and Vera systems before committing budget.