AMD disclosed the product stack for its EPYC 9006 "Venice" server processors this week, with the family topping out at 256 CPU cores fabricated on TSMC's 2nm process. The chips introduce the Zen 6 microarchitecture to the data center and form AMD's largest EPYC rollout to date, spanning four launch SKUs.

AMD released SKU lists alongside a whitepaper and its Advancing AI 2026 event. A fifth, AI-focused variant with LPDDR support arrives in 2027.

What does the Zen 6 CCD lineup look like?

AMD will produce two CCD chiplet variants for Venice: a high-performance Zen 6 die and a high-density Zen 6c die. Both variants share TSMC's 2nm process, a departure from Turin, where the two chiplet types used different nodes.

The density advantage of Zen 6c widens substantially. Dense Venice SKUs reach 256 cores, 64 more than the 192-core Turin Dense chips. At the high-performance end, the top Zen 6 chip ships with 96 cores, down from 128 in Turin.

That reshapes the core-count ratio across the family:

• Dense Venice configurations carry up to 2.66x the cores of high-performance SKUs
• Turin Dense topped out at a 1.5x advantage

Clock speeds tighten the gap further:

• Zen 6: 5.0 GHz top frequency
• Zen 6c: 4.1 GHz top frequency (up 400 MHz from Turin Dense)
• Cores per CCD: 12 (up from 8 in Zen 5 / Turin)
• Top Venice package layout: 8 CCDs + 2 IODs

How does the new IOD expand memory and I/O?

AMD pairs the Zen 6 CCDs with a redesigned I/O die. The most prominent change is memory: Venice carries 16 memory channels, up from 12 on Turin. DDR5 RDIMMs run up to 8000 MT/s; MRDIMMs push the bus to 12,800 MT/s.

Platform memory bandwidth figures AMD disclosed:

• 1 TB/s with DDR5 RDIMMs
• 1.6 TB/s with MRDIMMs

PCIe 6 and CXL 3.1 are both supported, doubling I/O bandwidth over Turin. A single Venice socket exposes up to 128 PCIe/CXL lanes in a 1P configuration.

What's new in cache and interconnects?

Zen 6 pairs every CCD with 4 MB of L3 cache per core, applied uniformly across Zen 6 and Zen 6c. Aggregate cache figures for the launch SKUs:

• Up to 384 MB L3 on high-performance EPYC 9006 parts
• Up to 1024 MB L3 on dense SKUs

Compared with Zen 5, per-core L3 cache doubles on dense chiplets while holding steady on regular chiplets.

AMD also aligned xGMI between Venice and the Instinct MI455X accelerator. The two lines now share the same xGMI flavor, enabling cache-coherent CPU-GPU links for the first time. Earlier EPYC generations linked CPUs and GPUs over PCIe, matching xGMI bandwidth at roughly 32 Gbps per lane but without coherency.

High-end Venice chips carry two IODs rather than one. AMD has not detailed the design's NUMA implications. The IOD itself stays on TSMC's 6nm node, unchanged from Turin.

What does the power envelope look like?

TDPs climb with the core counts:

• 600 W TDP for 192- and 256-core Venice SKUs (100 W above Turin's top)
• Up to 500 W TDP for high-frequency Zen 6 SKUs

Performance-per-watt versus Turin still rises, AMD says, but server TDPs continue their upward creep.

What's coming in 2027?

AMD confirmed an LPDDR-equipped Venice variant for 2027, the first EPYC chip with LPDDR memory. The part complements the Helios rack-scale system AMD introduced this summer around the MI450 accelerator series.