September 2026 preprint arXiv:2609.15326 from TU Munich, the University of Modena and Reggio Emilia (UNIMORE) and Applied Materials delivers a like-for-like comparison of A7 complementary FET (CFET) and A10 nanosheet FET (NSFET) technology nodes across cell parasitics, thermal behavior and chip-level aging.

The paper, titled "System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability," runs a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow on both process nodes. Authors: Mahdi Benkhelifa, Leon Mayr, Hadi Nour Eddine, Andrea Padovani, Luca Larcher and Hussam Amrouch.

How does the study isolate the technology differences?

The team fed both A7 CFET and A10 NSFET through identical device models. That setup strips out process tuning noise and leaves parasitic RC behavior as the controlled variable. The paper states: "Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow."

What sits inside the STCO flow?

Six linked stages make up the pipeline: calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion for accurate 3D parasitic RC extraction, full RTL-to-GDS implementation of an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation.

The cross-domain linking matters. GDS-to-TCAD conversion extracts 3D parasitics directly from layout, so the cell-level RC numbers reflect actual routing rather than estimated capacitance. The thermal stage then overlays those parasitics onto a full-chip power map.

Why pair the flow with an AI accelerator?

The RTL-to-GDS step targets an AI accelerator workload rather than a generic core. Realistic block-level placement, routing and clock distribution push the parasitic RC figures out of standalone-cell theory and into silicon-design territory. BTI aging then layers device degradation on top of the extracted network, so the final reliability numbers reflect combined electrothermal wear.

What changes for design teams weighing A7 against A10?

The work hands engineers a reproducible methodology rather than a buy recommendation. Teams can replay the flow against their own IP, swap workloads, and read out parasitic RC, thermal and BTI deltas without rebuilding the underlying device models. The publication date and open arXiv posting (arXiv:2609.15326) put the artifacts in reach of any group with TCAD and standard-cell toolchains.

Which institutions contributed what?

TU Munich drives the STCO methodology and the AI accelerator implementation. UNIMORE handles the BTI aging models and the multiphysics thermal analysis. Applied Materials contributes device characterization and calibration data for both A7 and A10 nodes. The combined author roster spans two universities and one equipment maker, a structure typical of process-design co-optimization work in advanced nodes.

Bottom line for toolchain owners

A7 CFET and A10 NSFET sit roughly two generations apart on the IRDS-style roadmap, but the paper's value rests on the flow, not the verdict. Standard-cell libraries, GDS-to-TCAD converters, thermal solvers and aging models now exist as one chained pipeline that any consortium or foundry customer can rerun on proprietary IP.