Test report DSG-3964 · Rev E · tested October 10, 2026

Edge AI SiliconDevice under test

M31 and Ambiq Build Low-Power Foundation IP for TSMC N12e

M31 and Ambiq have jointly developed low-power foundation IP for TSMC's N12e 12nm process, targeting ultra-low-power edge and battery-driven SoC designs.

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Amara Osei

Spec summary

  1. M31 and Ambiq developed low-power foundation IP for TSMC's N12e process
  2. The partnership targets ultra-low-power SoC design on a 12nm-class process node
  3. Ambiq specializes in ultra-low-power semiconductors; M31 supplies the foundation IP portfolio
  4. No timeline or licensing terms were disclosed in the announcement
M31, Ambiq Develop Low-power Foundation IP for TSMC N12e - EE Times Asia
Fig. AM31, Ambiq Develop Low-power Foundation IP for TSMC N12e - EE Times Asia — AI-generated

M31 and Ambiq have developed low-power foundation IP for TSMC's N12e process, according to an EE Times Asia report. The collaboration targets designs where power consumption, not peak performance, sets the ceiling of what silicon can achieve.

The announcement names three parties. M31, a foundation IP provider, supplies the process-specific IP portfolio. Ambiq, a specialist in ultra-low-power semiconductors, contributes its design methodology and application requirements. TSMC's N12e — a 12nm-class process variant optimized for edge and embedded applications — serves as the target node.

Why does foundation IP matter at 12nm?

Foundation IP — standard cell libraries, memory compilers, and general-purpose building blocks — sits below every SoC design. Its power and area characteristics propagate through the entire chip. On a low-power process variant such as N12e, poorly matched foundation IP can erase the process advantages at the system level.

That explains the structure of this partnership. Ambiq builds chips for battery-constrained and energy-harvesting applications, where every nanoamp of leakage counts. M31's libraries, characterized specifically for the N12e process, give Ambiq's designers a validated starting point tuned to that regime.

What does the collaboration cover?

The reported scope centers on:

  • Low-power foundation IP developed jointly by M31 and Ambiq
  • Implementation on TSMC N12e, TSMC's 12nm low-power process offering
  • Support for ultra-low-power and edge SoC designs of the type Ambiq ships commercially

Who benefits?

The arrangement matters most to designers of edge AI devices, wearables, smart sensors, and other systems that must run for years on small batteries or harvested energy. Process nodes in the 12nm class offer a compromise: sufficient density and performance for edge inference workloads, at a cost and maturity level that suits high-volume consumer and industrial products.

For fabless companies, qualified foundation IP on a proven node reduces both schedule risk and verification effort. Instead of characterizing libraries in-house, teams can license blocks already validated against silicon on N12e.

For TSMC, ecosystem support of this kind extends the commercial life of its specialty process variants. N12e gains a stronger IP story, which makes the node viable for a wider set of customers.

The competitive context

Ultra-low-power design has become a contested segment as edge computing volumes grow. Companies such as Ambiq compete on the energy efficiency of their silicon, and process-plus-IP combinations are one of the main levers for gains in that metric. Foundation IP tuned jointly by an IP vendor and an end-product silicon company signals that both parties expect the resulting libraries to meet production requirements, not merely research benchmarks.

No timeline for broader IP availability, licensing terms, or first customer silicon was included in the announcement as reported.

Die Signal will follow up as M31, Ambiq, or TSMC disclose additional technical detail on the N12e foundation IP offering.

via Google News: TSMC (Source)

Filed under

  • m31
  • ambiq
  • tsmc
  • n12e
  • foundation-ip
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Amara Osei

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Staff writer covering business strategy at Die Signal.

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