Synopsys has completed A14-class electronic design automation (EDA) certification with TSMC and taped out a 64 gigatransfers per second (GT/s) UCIe testchip on TSMC's 2nm and 3nm processes, with the supporting IP portfolio adding PCIe 7.0 and HBM4 controller and PHY blocks.

What does the A14 certification include?

The certification covers Synopsys' digital implementation toolchain — synthesis, place-and-route, timing analysis, and sign-off — validated against TSMC's A14 process design kit. A14 sits ahead of TSMC's N2 (2nm) generation in the foundry's public roadmap and uses gate-all-around nanosheet transistors. Joint customers can now begin silicon implementation on A14 within TSMC's design rules using the Synopsys flow.

Until EDA certification lands, most designs targeting a new node remain at the paper-study stage. Synopsys' A14 qualification puts it in line with competing offerings from Cadence and Siemens EDA, both of which have announced TSMC A14 collaborations in recent quarters.

What does the 64G UCIe tape-out cover?

The 64 GT/s UCIe (Universal Chiplet Interconnect Express) link is the highest data rate in the UCIe specification; it doubles the per-lane throughput of the standard's 32 GT/s configuration. UCIe is the leading open-standard die-to-die interconnect and forms the basis of most announced chiplet-based processors and accelerators.

The tape-out runs Synopsys' UCIe controller and PHY on TSMC's 2nm (N2) and 3nm (N3) processes. N3 entered volume production in late 2022. N2 entered risk production in 2025 and is set to ramp toward high-volume manufacturing. Silicon-proven UCIe IP at 64 GT/s on both nodes removes a re-spin risk for AI accelerators and disaggregated CPUs targeting those processes.

What about PCIe 7.0 and HBM4?

The IP bundle announced with the tape-out adds three high-speed interface families:

• PCIe 7.0: Controller and PHY. The specification, finalized by the PCI-SIG, delivers 128 GT/s in an x16 configuration — a doubling over PCIe 6.0's 64 GT/s.
• HBM4: Controller and PHY. JEDEC's high-bandwidth memory standard supports 2048-bit interfaces operating above 1.5 TB/s per stack.
• UCIe: Controller and PHY at standard and advanced package speeds, including the 64 GT/s mode.

The trio gives customers a single-vendor path between logic on advanced nodes, stacked HBM4 memory, and PCIe 7.0 expansion — the three IP blocks now standard in most AI accelerator and switch designs.

What changes for chip designers?

Two practical outcomes follow:

• Customers targeting TSMC A14 can run an EDA-certified flow immediately, rather than wait for restricted or beta PDK access.
• Customers building chiplet products on 2nm or 3nm can license silicon-validated UCIe IP at 64 GT/s, avoiding a first-pass silicon re-spin on the interconnect layer.

Both compress design cycle time. The combination also raises the competitive floor for EDA and IP vendors: keeping pace with TSMC's leading-edge roadmap, which has compressed from roughly two years between major nodes toward 18 months at the cutting edge, now requires synchronized certification across multiple vendors.