TSMC CoWoS Prices May Rise Up to 20% as AI Chips Strain Packaging

Quoted prices for TSMC's CoWoS advanced packaging could rise by as much as 20%, according to a October 27, 2026 report from Taiwan's Commercial Times citing anonymous supply chain sources. That's the headline number, but practitioners should read it carefully: it's a reported ceiling for quoted prices, not a confirmed transaction-price increase, and TSMC has made no official announcement.

What does the report actually say?

The paper describes two separate figures with different scopes:

• Up to 20% for TSMC's CoWoS quoted prices
• 10–20% adjustments under discussion across the wider foundry and OSAT (outsourced assembly and test) industry

Neither baseline prices nor post-revision prices are disclosed. The report doesn't specify timing, which customers are covered, or how long-term contracts would be treated. Where large customers hold fixed pricing terms, a revision of quoted prices for new orders wouldn't automatically flow through to existing contracts. Nothing confirms any customer has accepted an increase.

In the semiconductor trade, tight supply often prompts manufacturers to ask customers to revisit quotes — partly to curb excess orders, partly to fund capital investment. The "up to 20%" figure is best read as a demand signal, not a settled price hike.

Why is capacity tightening?

CoWoS is TSMC's 2.5D packaging family, placing multiple logic dies and HBM stacks in one package. The variants matter: CoWoS-S uses a silicon interposer and supports up to about 2,700 mm² — roughly 3.3 times lithography reticle size. CoWoS-R, in mass production since 2023, uses an organic redistribution layer. CoWoS-L combines RDL with localized silicon bridges; a 3.5x-reticle configuration entered mass production in 2024, and 5.5x-reticle packages are now in production per TSMC's 2026 North America Technology Symposium materials.

Equipment makers interviewed by the paper explain the squeeze plainly: larger packages mean fewer units per wafer, more complex die-and-HBM bonding, harder-to-control warpage, and longer test times. That burdens both packaging and testing stages simultaneously.

How fast can supply respond?

Not fast. Industry sources say a new advanced packaging plant takes about three years from groundbreaking to fully operational equipment. Equipment delivery lead times have stretched from roughly 3–6 months to 6–8 months, and toolmakers themselves face component shortages — constraints money alone can't resolve.

External analysts forecast TSMC's CoWoS wafer capacity exceeding 130,000 wafers per month in 2026 and reaching 200,000 in 2027. The planned US "AP1" packaging plant is reported to start operating in 2028. These are estimates, not TSMC commitments, and wafer throughput can't be converted directly into finished packages as areas grow.

TSMC acknowledges the gap. At the October 15, 2026 earnings call, Chairman and CEO C.C. Wei said the demand-supply gap for advanced packaging, including CoWoS, is "very large," without quantifying it. He also said 5-reticle packages are in volume production with "excellent" yields. The 2026 capex plan holds at $60–64 billion, though most goes to advanced logic fabs, not CoWoS specifically.

Can Intel's EMIB substitute?

Intel's EMIB embeds silicon bridges in an organic substrate and has shipped in volume since 2017. Its March 2026 roadmap targets over 8 reticles (~6,800 mm²) in 2026 and over 12 reticles (~10,000 mm²) by 2028, with EMIB-T adding TSVs beyond 6 reticles.

Switching is another matter. NVIDIA and AI-ASIC developers have design flows, IP, HBM configurations, and inspection methods built around CoWoS. Requalification could take six months to a year or more and delay launches. Even at 10–20% higher CoWoS prices, staying put may be more rational once switching costs and delay risks are counted.

What does it mean for chip prices?

A 20% packaging cost increase doesn't translate one-for-one into AI accelerator prices. Packaging is one slice of a bill of materials that includes logic wafers, HBM, boards, power, and cooling. Whether chipmakers absorb or pass on costs depends on contracts and competition.

Watch for these indicators: an official TSMC price announcement, capex allocation to packaging, plant start-ups, equipment lead times, and whether TSMC's 14-reticle CoWoS target for 2028 — carrying roughly 10 compute dies and 20 HBM stacks — stays on schedule.