Cadence Design Systems and TSMC have jointly announced a collaboration covering certified EDA tool solutions and silicon-proven UALink intellectual property on TSMC's advanced process technologies.

The partnership, reported by Yahoo Finance, spans two product streams. Cadence will provide certified EDA tool flows qualified to TSMC's process design kits, alongside a silicon-proven UALink IP block for chip designers targeting TSMC's advanced nodes. The release does not list which specific TSMC process nodes the collaboration covers, nor does it include release dates, pricing, or named customer designs.

What does the announcement cover?

The certified tool solutions stream covers Cadence's digital implementation, signoff, and verification tools. Certification against a foundry's PDK lets chip designers run those tools with a vendor-backed signoff path, which removes the in-house qualification work that each tool release would otherwise demand. The UALink IP stream delivers a pre-verified die-to-die interface block that designers integrate into an SoC floorplan, which reduces the engineering effort and tape-out risk of a custom die-to-die interface.

What is UALink?

UALink is an open die-to-die interconnect standard targeting accelerator-to-accelerator and accelerator-to-switch links inside AI compute systems. The UALink Consortium, whose members include AMD, Intel, and Broadcom, maintains the specification. Cadence's silicon-proven block has taped out on a real TSMC process, giving chip designers a hardened macro they can drop into an SoC layout instead of building a die-to-die interface from the specification.

Why does certification matter for tool buyers?

A certified EDA tool flow means the vendor has qualified the tools against the foundry's process design kit and reference flow. Customers targeting those processes can sign off chips with a vendor-backed path, shortening tool qualification cycles across process revisions. Qualification is process-specific, so each TSMC node requires its own certification pass.

Why does the UALink piece matter?

AI accelerator and switch chips depend on die-to-die interfaces to scale out compute across multi-chip packages. Designers weighing UCIe, UALink, and proprietary formats compare them on bandwidth, latency, ecosystem support, and IP availability. A silicon-proven UALink offering from a top-three EDA vendor on TSMC's advanced nodes adds a qualified option to that comparison.

What is missing from the announcement?

The release did not specify the TSMC process nodes covered, the UALink lane configuration supported, power and area figures for the IP, license terms, or tape-out commitments from named customers. Neither Cadence nor TSMC had published the full press release on their corporate sites at the time of writing.