Intel raised Diamond Rapids' core count from 192 to 256 in roughly three months, bringing the upcoming Xeon to core-count parity with AMD's recently launched Venice at the Hot Chips 2026 conference.

What did Intel change between Computex and Hot Chips?

At Computex, Intel positioned Diamond Rapids with 50% more cores than Granite Rapids, double the memory bandwidth, and PCIe Gen 6 support. The original 192-core figure corresponded to that 50% uplift. Hot Chips 2026 disclosures push that number to 256 cores.

The revised specifications:

• 256 cores (up from 192)
• 1.6 TB/s memory bandwidth, double Granite Rapids
• 128 PCIe Gen 6 lanes
• 320 MB of 3D-stacked L3 cache per base tile

How does Diamond Rapids stack against AMD Venice?

Diamond Rapids now matches AMD Venice on two key metrics: core count (256) and memory bandwidth (1.6 TB/s on the SP7 platform). Intel holds a PCIe edge with 128 Gen 6 lanes versus SP7's 96 lanes. Memory bandwidth also doubles what Granite Rapids delivered.

What does the die layout look like?

Intel built Diamond Rapids with 4 base dies and 2 I/O tiles. Compute chiplets sit on the edges of the I/O dies, mirroring AMD's Venice topology. Each base die carries 320 MB of 3D-stacked L3 cache. Core chiplets hold only cores and L2 cache. AMD's optional V-Cache dies do not appear on Diamond Rapids. Every compute tile stacks L3 onto the base die by design.

Why did Intel drop 2.5D packaging?

Intel chose UCIe-S (Standard) packaging at 16 gigatransfers per second over 2.5D. The switch lets each base die reach both I/O dies. 2.5D wires cannot span the distance to both I/O tiles.

At 16 GT/s, each base die needs roughly 400 pins to its I/O die to drive the full 1.6 TB/s memory throughput. The dual I/O dies need approximately 1,800 pins between them to split memory and PCIe bandwidth evenly.

What new ISA extensions ship with Diamond Rapids?

Diamond Rapids introduces two x86 extensions.

• AVX10.2 folds the AVX-512 flavors found in Granite Rapids into one envelope and adds new instructions. Nova Lake client silicon will also support AVX10.2.
• APX (Advanced Performance Extensions) marks the first major scalar x86 addition since AMD64. APX adds 16 general-purpose registers, lifting x86 to 32 GPRs. APX also introduces three-operand instructions, conditionals, and broader branch support.

What did Intel leave unanswered?

Hot Chips slides did not address clock speeds, power consumption, pricing, or sustained all-core performance. UCIe-S bandwidth raises its own questions about latency and yield at production volumes.

In three months, Diamond Rapids moved from "clearly behind" on paper to "competitive" on paper. Independent silicon benchmarks will determine whether that paper performance holds. Independent testing with all 256 cores loaded remains pending.