Test report DSG-9352 · Rev A · tested October 8, 2026
Processors & AcceleratorsDevice under test
Xsight Labs E1L Scales 200Gbps DPU Down to 25W Envelope
Xsight Labs' E1L DPU pairs 8-22 Arm Neoverse N2 cores with 200Gbps throughput in a 25-40 W TDP, targeting switches, storage servers and control planes where power limits rule.
- Read
- 3 min
- Words
- 592
- Node
- 3nm
- Operator
- Amara Osei
Spec summary
- The E1L DPU offers 8, 16 or 22 Arm Neoverse N2 cores with up to 200Gbps over 4x SerDes lanes.
- Configurable TDP is 25 W, 30 W or 40 W, with typical draws of 15 W, 18 W and 25 W.
- The design runs on a COM Express Type 7 module suited to network switches and storage servers.
- It provides line-rate AES-GCM for IPsec offload and 20x PCIe Gen5 lanes with SR-IOV support.
- Xsight positions the part as a lower-power sibling of its 64-core 800Gbps E1 DPU.

Xsight Labs has announced the E1L DPU, a 200Gbps part with a configurable TDP of 25 W, 30 W or 40 W — and typical draws of just 15 W, 18 W and 25 W respectively. The company positions the chip as a lower-power alternative to its own 64-core E1 DPU, targeting deployments where power, not peak bandwidth, is the binding constraint.
What are the key specifications?
The E1L fills a deliberately modest power envelope while keeping the architecture of its larger sibling:
- 8, 16, or 22 Arm Neoverse N2 cores
- Up to 200Gbps over 4x SerDes lanes
- Up to 2x DDR5-5200 interfaces with inline encryption
- Line-rate AES-GCM for IPsec offload
- 20x PCIe Gen5 lanes across 6x dual-mode controllers with SR-IOV support
- Configurable TDP of 25 W, 30 W or 40 W, with typical draw of 15 W, 18 W and 25 W
The design runs on a COM Express Type 7 module. That form factor choice points directly at network switches, where a full-size DPU card is neither practical nor desirable from a thermal standpoint. Storage servers are the second obvious target. The E1L could theoretically attach E1.L SSDs to its PCIe lanes, allowing an entire system to be built around E1L/E1.L components.
How does the philosophy differ from AMD Pensando?
Xsight takes the opposite architectural position to AMD. AMD argues that running network offloads via Linux and DPDK across many Arm cores is the wrong approach, and builds its Pensando DPUs around P4 programmable engines instead. Xsight bets on exactly that Arm-core-plus-software model.
The Neoverse N2 implementation on the E1 is deliberately vanilla. STH has previously demonstrated installing out-of-the-box Ubuntu LTS on the Xsight Labs E1 64-core Arm 800G DPU. Standard Linux tooling runs without porting work, and that software path carries over to the E1L unchanged.
How does Neoverse N2 perform?
STH charted single-core results from its AgentSTH V7 workloads to give a sense of relative performance against other platforms. The single-core score was chosen because the E1 DPU carries 64 cores, and a multi-core comparison would skew the picture.
Memory constraints prevented a BlueField-2 DPU from running AgentSTH V7. For context, BlueField-4 is based on the Neoverse V2 core found in the Grace CPU, likely at higher clocks in the GB300 part shown in the comparison chart. The large multi-core delta between parts reflects the E1's 64 cores and newer architecture.
An 8-22 core part remains very capable for storage workloads, switch control planes and virtualization hosts.
Why scale down instead of up?
Most of the industry is chasing 800Gbps and higher speeds. Xsight Labs is moving the other way: it takes its 800Gbps design and scales it to 200Gbps. The power reduction matters more than the bandwidth cut, because it opens application categories where hitting 800Gbps was never the goal.
There is also an architectural argument. Because the company uses Neoverse N2 Arm cores with DPDK and other standard Linux features, an acceleration path that runs at 800Gbps on the 64-core E1 should scale down easily to the lower-core-count E1L. Software written for the big part carries over; the same cannot be said for designs that depend on fixed-function or domain-specific programmable engines.
The E1L is, in effect, the same design point shrunk to fit a switch slot or a dense storage node — a segment where a 15 W typical draw beats an 800G headline every time.
via ServeTheHome (Source)
More from Amara Osei
Same lot · LOT-C1AF
- DSG-124314nmAMD EPYC 9006: Mapping Venice Silicon to Agentic AI Workloads
- DSG-668820nmArm's C2-Ultra, G2-Ultra NX and Neoverse CSS N4: The Numbers Behind the Claims
- DSG-813665nmZella DC Launches Stackable Micro Data Center Line for Edge Deployments
- DSG-589520nmAMD EPYC Verano Reportedly Targets 72 Zen 6 Cores on New SB1 Socket
- DSG-425365nmTesla Cuts AI5 Chip Memory to 72GB as DRAM Supply Tightens