Synopsys and TSMC have expanded their collaboration to bring Synopsys' design intellectual property (IP) to TSMC's 2nm node, with the work explicitly framed around agentic AI systems.

The extension covers Synopsys' interface and controller IP catalog — including UCIe chiplet links, DDR and HBM PHYs, and PCIe connectivity — now certified for TSMC's N2 process. Both companies positioned the announcement as targeting data center AI accelerators running agentic AI inference workloads.

What does agentic AI change in silicon requirements?

Agentic AI systems execute multi-step tasks — planning, tool use, retrieval, and persistent memory — rather than producing single-shot model outputs. That workload mix shifts chip demand toward higher memory bandwidth, larger cache hierarchies, and tighter die-to-die links across multi-chiplet packages. The shift raises the value of process-level power efficiency over raw peak FLOPs, since each inference token in an agentic loop carries overhead from memory access and inter-chip traffic.

Why N2 specifically?

TSMC's N2 node uses gate-all-around (GAA) nanosheet transistors, replacing the FinFET architecture used in N3 and earlier processes. Nanosheet devices deliver better short-channel control, allowing higher drive current per unit area and lower power at equivalent performance versus the prior generation. The 2nm designation also signals the end of FinFET scaling across the industry, with all major foundries now committed to GAA at the leading edge. TSMC has indicated that a subsequent N2P variant will introduce backside power delivery, reducing IR drop on power-hungry AI dies.

For agentic AI workloads, where accelerators spend significant time waiting on memory and interconnect rather than computing, those efficiency gains translate directly into usable tokens per second per watt. They also enable higher accelerator counts per rack under fixed power budgets.

How does Synopsys fit?

Synopsys supplies physical IP, EDA tools, and verification platforms used by most fabless AI accelerator designers. Certifying interface IP at a new process node typically spans multiple quarters of co-development with the foundry, covering PPA (power, performance, area) characterization, design-rule compliance, and silicon-validated reliability across voltage and temperature corners.

Bringing the IP catalog to N2 lets customer chip teams integrate pre-validated blocks rather than qualifying them internally, compressing time-to-tape-out for next-generation AI silicon. The same blocks typically require re-validation at each new node, so this announcement effectively shifts a year of engineering effort from each customer onto Synopsys' pre-existing roadmap.

Market context

Synopsys and TSMC have co-developed IP for multiple process generations, with prior releases covering N5, N4, and N3 variants. The N2 expansion extends a partnership that effectively sets the floor for what fabless AI chip designers can integrate at each new node without running their own silicon validation cycles. For AI accelerator startups without captive IP teams, the certified catalog often decides whether a tape-out stays on schedule at all. Established vendors with in-house PHY teams still buy Synopsys IP for risk reduction and second-source flexibility.

Competitive angle

Foundry competitors Samsung Foundry and Intel Foundry Services pursue parallel 2nm-class roadmaps — Samsung's SF2 and Intel's 18A — both also targeting GAA architectures. Synopsys historically maintains IP programs across all major foundries, but certification depth varies. AI accelerator vendors with foundry flexibility may now compare not only wafer economics but also the breadth of certified physical IP available at each node. That comparison will intensify as the three leading 2nm-class nodes all reach volume manufacturing.

What remains unconfirmed

The report did not specify which Synopsys IP blocks lead the N2 certification, whether HBM4 PHYs are included, or how N2 IP licensing compares with N3 and N5 tiers. Customer chip teams evaluating the catalog for upcoming agentic AI accelerators will need those details before committing to N2 tape-outs.