TSMC North America CEO Sajiv Dalal told attendees at the company's Open Innovation Partners North America Technology Symposium that worldwide semiconductor revenue will reach approximately $1.7 trillion by year-end 2026, with AI chips alone accounting for more than $1 trillion of that figure.

The trajectory marks a sharp upward revision from the ~$1 trillion by 2030 forecast TSMC's Kevin Zhang presented at ISSCC in January 2024.

How does the new number compare with the 2024 forecast?

Zhang's 2024 ISSCC slide projected worldwide chip revenue at roughly $1 trillion by 2030. Dalal's 2026 outlook covers the same dollar figure inside a single calendar year. Gartner's parallel forecast of about $1.6 trillion for 2026 sits within the same band, lending independent weight to TSMC's revised trajectory.

The revision is anchored to the AI build-out. Compute, memory density and power demand are all moving in the same direction, accelerating the revenue curve.

What does TSMC's own revenue data show?

The August 2026 revenue update places TSMC at a 53.3% year-over-year increase. Comparable January-to-August figures for 2025 and 2026 show a 39.3% gain. The August update overlays TSMC process and product milestones with the steepening revenue curve of the AI era.

How are advanced nodes keeping pace with demand?

Li-Pen Yuan, TSMC vice president of business development, said the number of new tape-outs in the second year of a node has increased by 4× across N5, N3 and N2. Yuan characterized the figure as a massive acceleration in designs targeting N2, beyond the new-design rate already set by N3.

Growth spans segments. HPC/mobile, automotive and IoT each project separate upward curves in TSMC's node roadmap.

What do the AI workload numbers look like?

L.C. Lu, TSMC senior fellow and vice president for design and technology platforms, said inference token usage has grown 500× over the past three years. "Inference is becoming the growth driver for AI," Lu told the audience.

Demand cascades into power. Lu framed power scaling as an extension of Moore's Law. On TSMC's A14 Nanoflex, cell height moves to 1.5× from the previous generation's 2×, with a 14% speed improvement and 23% power reduction versus N2P. From N3P to A12 SPR, HPC cell power efficiency rises 2.3×.

How is memory and interconnect scaling?

Lu presented a memory figure of merit defined as the product of transistor count and speed at power. That benchmark will rise 87× by 2029. Bandwidth gains over the next five years reach 34× for HBM, 115× for 3D DRAM, and 830× for SRAM.

Energy-per-bit by 2029 is projected at 0.32 pJ/bit for SRAM, 1 pJ/bit for 3D DRAM, and 2.5 pJ/bit for HBM.

For interconnect, TSMC's COUPE silicon photonics platform targets serial data rates of 224G and 448G, with multiple wavelengths per fiber multiplying aggregate bandwidth.

Which ecosystem partnerships did TSMC highlight?

imec joined as a new partner. IC-Link by imec earned a partner-of-the-year award after integrating into the OIP Cloud Alliance as its first managed-cloud service for mixed-partner EDA workflows. Amazon Web Services and Microsoft Azure also won in this category. Cadence, Siemens EDA and Synopsys took the EDA partner-of-the-year awards.

To bring AI into chip design itself, TSMC is rolling out AI Design Kits (ADKs) and working with partners on agentic-AI-driven design flows. The framework TSMC presented uses AI to build the chips needed for AI workloads.

Greg Dix, vice president of engineering for Broadcom's ASIC Products Division, described the velocity this enables. He said OpenAI's Jalapeno custom AI ASIC went from project kick-off to tape-out in nine months. "The SoC era is ending and SiP is accelerating," Dix said at OIP.

That compressing design-to-tape-out window, combined with a $1.7 trillion industry target, sets the operating tempo for the rest of 2026.