Test report DSG-2064 · Rev C · tested October 10, 2026
Foundries & ManufacturingDevice under test
TSMC Lifts 2026 Chip Revenue Forecast to $1.7T, Anchored by AI
TSMC projects global chip revenue of $1.7 trillion by year-end 2026, with over $1 trillion from AI. Inference token usage has grown 500x in three years, N2 tape-outs quadruple, and memory bandwidths set to climb 830x for SRAM by 2029.
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Spec summary
- TSMC projects global semiconductor revenue of $1.7 trillion by end of 2026, with more than $1 trillion from AI alone
- TSMC revenue rose 53.3% year-over-year; January-to-August 2025 vs 2026 totals rose 39.3%
- Inference token usage grew 500 times over the past three years, per TSMC's L.C. Lu
- Memory bandwidths are projected to increase 34x for HBM, 115x for 3D DRAM, and 830x for SRAM over five years
- OpenAI's Jalapeno custom AI ASIC reached tape-out in nine months from project kick-off, per Broadcom's Greg Dix
Global semiconductor revenue will reach approximately $1.7 trillion by the end of 2026, with more than $1 trillion of that total coming from artificial intelligence alone, according to TSMC North America chief executive Sajiv Dalal. Speaking at TSMC's Open Innovation Partners North America Technology Symposium, Dalal framed the figure as a near-term milestone rather than a long-horizon target. The number aligns with the analyst's projection of about $1.6 trillion for the industry in 2026.
At the 2024 ISSCC, TSMC's Kevin Zhang had projected worldwide semiconductor revenue reaching roughly $1 trillion by 2030 — a forecast Dalal's team has now pulled forward by four years. TSMC's recent revenue figures show a 53.3% year-over-year increase, while comparable January-to-August totals for 2025 and 2026 reflect a 39.3% rise.
What does the new outlook change?
The shift places AI at the structural center of chip demand rather than as a tailwind layered on top of existing growth. "Inference token usage has grown 500 times over the past three years and inference is becoming the growth driver for AI," said L.C. Lu, TSMC senior fellow and vice president for design and technology platforms.
Lu added that power scaling extends Moore's Law. The figures he presented on the A14 Nanoflex node versus N2P:
- Cell height moves to 1.5 times, compared with 2 times for previous nodes
- 14% improvement in speed
- 23% reduction in power
High-performance-computing cell power efficiency improves 2.3 times when moving from N3P to A12 SPR, according to the same presentation.
Where is the design activity concentrating?
Li-Pen Yuan, vice president of business development at TSMC, said the number of new tape-outs had increased fourfold as measured by the second year of a new technology across the N5, N3, and N2 nodes. The report described a substantial acceleration in new designs targeting the N2 technology, continuing beyond the higher design rate already seen at N3.
Forecast growth was also presented across high-performance computing, mobile, automotive, and IoT segments.
How fast does memory have to move?
Lu presented a figure of merit based on transistor count multiplied by speed at a given power level. The benchmark is expected to increase 87 times in 2029 based on predicted improvements from technology advancements.
Bandwidth projections over five years:
- HBM: 34x
- 3D DRAM: 115x
- SRAM: 830x
Energy-per-bit forecasts for 2029 stand at 0.32 picojoules per bit for SRAM, 1 pJ/bit for 3D DRAM, and 2.5 pJ/bit for HBM.
What does TSMC-COUPE add to the roadmap?
TSMC's COUPE platform targets energy-efficient high-speed communication as serial data rates rise to 224G and 448G. Its future roadmap includes continued increases in gigabits-per-second serial data rates, with the ability to incorporate multiple wavelengths per fiber to raise overall fiber bandwidth.
How fast are custom AI ASICs moving?
Broadcom's Greg Dix, vice president of engineering for the ASIC Products Division, said the OpenAI Jalapeno custom AI ASIC went from project kick-off to tape-out in nine months. Dix also said the system-on-chip era is ending and that system-in-package is accelerating.
Who won the partner awards?
TSMC recently added imec as a partner. IC-Link by imec received a partner-of-the-year award after integrating into the OIP Cloud Alliance as its first managed-cloud service supporting mixed-partner EDA workflows. Amazon Web Services and Microsoft Azure also won in that category. EDA partners of the year went to Cadence, Siemens EDA, and Synopsys.
AI is now operating in a positive feedback environment, where advances in AI produce new tools and productivity gains in the development of further AI technologies — a loop the symposium participants said TSMC is engineering into its design flows through AI Design Kits and AI-driven flows developed with partners.
via app.indexbox.io (Original)
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Senior reporter covering industry trends and analytics at Die Signal.
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