By Grace Kim

SK Hynix has introduced a new memory tier that sits above HBM (high-bandwidth memory, the stacked DRAM used on AI accelerators): 3D stacked DRAM mounted directly on the processor die. The announcement shifts where memory lives — from a package next to the logic chip to a layer bonded on top of it.

That's the core of it. Instead of HBM dies sitting beside the GPU or ASIC on an interposer, the new tier stacks DRAM on the processor itself. It's a hierarchy change, not just a faster part.

What does this change for system designers?

Distance. Signal paths between logic and memory shrink from millimeters across a package to the thickness of a bonding layer. Shorter paths mean the potential for higher bandwidth and lower energy per bit than HBM can reach, simply because the physics get easier.

The catch is capacity. Memory stacked on the die competes with heat removal; DRAM on top of the processor sits directly in the thermal path. Cooling a logic die through a DRAM stack is a hard problem, and it's why this tier complements HBM rather than replacing it. Think small, fast, close memory — with HBM and conventional DRAM still carrying the bulk capacity below it in the hierarchy.

Where it fits

The tier structure now runs:

• On-die caches (SRAM) — fastest, smallest
• 3D stacked DRAM on the processor die — the new tier
• HBM — stacked DRAM beside the logic on package
• Conventional DRAM (DDR) on modules

SK Hynix positioned the technology as a tier above HBM in bandwidth terms, not a successor. The company didn't announce product timelines, capacities, or bandwidth figures alongside the introduction.

Why now

AI accelerators are bandwidth-starved. Models keep growing, and the energy cost of moving data between HBM and compute now dominates the cost of the arithmetic itself. Every layer of the stack that moves memory closer to logic cuts that movement cost.

SK Hynix, as the leading HBM supplier to AI chipmakers, has both the incentive and the stacking-process expertise to push the next step. 3D stacking of DRAM on logic builds on the same wafer-bonding techniques (joining processed wafers or dies vertically) that made HBM possible.

The open questions

No dates, no customers, no specs yet. What exists today is a technology introduction and a hierarchy claim. Watch for three things: thermal solutions that let a processor draw full power under a DRAM stack, yield economics on bonded logic-plus-DRAM wafers, and which accelerator vendor signs on first.

Until then, HBM remains the workhorse. The new tier is a bet on where the bandwidth wall forces the industry next.