By Grace Kim

Samsung and SK Hynix have opened a two-front race over HBM4, the next generation of high-bandwidth memory (HBM, stacked DRAM chips wired to a GPU's compute die), and they've picked different hills to fight on. Samsung is chasing speed. SK Hynix is going taller.

That's the split Tech Times reports at the heart of Korea's AI memory war: one camp pushing faster HBM4, the other pushing greater stacking height — more DRAM layers per package — to win the accelerators that NVIDIA and its rivals will ship next.

It's a fork in the road, not a detour. Both companies need HBM4 wins because AI accelerators are the only part of the memory market growing fast enough to matter right now. Whoever supplies the next generation of NVIDIA's training GPUs owns the premium tier of the industry for years.

What does this change for buyers?

Faster base dies mean more bandwidth per stack. Taller stacks mean more capacity per stack. A data-center operator shopping for training clusters cares about both, but not equally: bandwidth limits how fast a GPU eats data, capacity limits how big a model fits on one machine.

So the split matters. If Samsung's speed-first HBM4 lands first, bandwidth-hungry workloads get relief sooner. If SK Hynix's taller stacks arrive first, capacity-constrained deployments do. Either way, the customer wins a规格 race the two suppliers are now running in public.

Why stacking height is the hard part

Going taller sounds trivial. It isn't.

Each HBM package stacks multiple DRAM dies on a base logic die, connected through vertical wires called through-silicon vias (TSVs). Add layers and you add TSV count, heat, warpage risk, and yield loss. Every additional die multiplies the chance one of them is defective, and a single bad layer can scrap the whole stack.

That's why stack height has historically been a bragging-rights metric in HBM. Getting more layers into the same package, at yields that keep the price per gigabyte sane, is where the engineering money goes.

Why speed is the other hard part

HBM4 raises the interface width of the memory bus compared with HBM3 and HBM3E (the current shipping generation), which means more signal-integrity work at higher clock speeds. Faster HBM4 demands tighter timing across every die in the stack, not just the interface.

Speed-first designs trade that pain for raw throughput. It's the same bet GPU makers have made for a decade: bandwidth per watt is what sells accelerators, and memory is now the bottleneck, not compute.

What we still don't know

Be clear about the limits of what's public. Neither company has published, in this report, detailed HBM4 specifications, volume timelines, or named customers. What's on record is the strategic posture: Samsung leaning on speed, SK Hynix leaning on stack height.

The verification comes when qualification results do — when accelerator vendors announce which HBM4 variant clears their test suites, at what capacity, and in whose shipments. Watch NVIDIA's supplier disclosures. That's where the war gets scored.

Until then, the split tells you where each Korean giant thinks the risk lives. Samsung bets the bottleneck is bandwidth. SK Hynix bets it's capacity. Both can't be equally right, and the AI hardware market will render its verdict in purchase orders.