SEMIFIVE has signed a USD 52 million contract to deliver an AI accelerator design for an unnamed U.S. fabless semiconductor company, the company announced.

The figure marks the largest publicly disclosed AI accelerator design engagement for SEMIFIVE and provides a commercial benchmark for the company's end-to-end ASIC service offering in the North American market.

What does the deal cover?

The contract covers the design of a custom AI accelerator for the U.S. customer. SEMIFIVE will execute the project under an end-to-end model running from chip specification through silicon delivery. The fabless customer retains ownership of the resulting silicon.

Why does this matter for SEMIFIVE?

The $52 million figure provides commercial validation of SEMIFIVE's end-to-end ASIC service model in North America. The company has built its offering around reusable platform IP designed to compress design cycles for AI, high-performance computing, and other custom-silicon applications. A deal of this scale with a U.S. fabless customer signals that platform-based design services can compete with traditional ASIC engagement models dominated by larger service vendors.

The U.S. fabless ecosystem includes hyperscalers developing custom AI training and inference chips, automotive Tier-1s, and a growing cohort of AI-focused startups. Landing a $52 million program with a buyer in this cohort provides SEMIFIVE with a reference case that is commercially defensible and technically verifiable.

The North American win carries particular weight because the U.S. fabless market remains the largest single customer base for advanced-node AI silicon. Establishing a reference deployment of this size creates a path for follow-on engagements with similar buyers.

What is an end-to-end ASIC model?

End-to-end ASIC engagements bundle the full custom-chip development flow under a single vendor. The scope typically includes architecture definition, logic design (RTL), functional verification, physical design, and tape-out coordination, with the design house carrying engineering risk across the program. The model contrasts with point-service engagements, where customers assemble IP, design, and manufacturing support from separate providers.

In SEMIFIVE's case, the platform-based approach centers on pre-verified subsystems and a configurable SoC architecture that the design services team adapts to customer workloads. This reduces front-end design time and lowers the risk of late-stage re-spins, which can dominate ASIC program costs.

What does the figure signal for the AI accelerator market?

A $52 million design services contract for a single AI accelerator program points to the rising cost and complexity of custom AI silicon. Hyperscalers and AI-focused fabless companies are increasingly funding dedicated accelerator designs rather than relying on general-purpose GPUs alone. Design service vendors with proven platform IP and tape-out experience are positioned to capture portions of that spend.

The contract value also indicates the scale of NRE required to bring a competitive AI accelerator to production on an advanced process node, where mask sets and IP licensing alone can run into the tens of millions of dollars.

Such contracts are typically structured as fixed-fee NRE with optional royalty components tied to wafer volumes. A $52 million figure implies either a high-complexity multi-die package or a high-margin engagement, both of which narrow the field of qualifying service vendors.

What remains undisclosed

The release does not name the U.S. fabless customer, identify the target process node, or provide a tape-out or delivery timeline. SEMIFIVE has not indicated whether the $52 million includes production-volume royalties or covers a non-recurring engineering (NRE) arrangement.