K-Cloud targets mixed Korean AI chips in one data center

By Grace Kim

K-Cloud’s third-year plan calls for installing multiple neural processing units (NPUs) and data processing units (DPUs) in one server, then pooling inference, training and Compute Express Link (CXL) memory resources for a data-center-scale system.

At K-Cloud Tech Day 2026, held on the 27th at Seoul AI Hub in Seocho-gu, Seoul, HyperAccel and the Institute of Information & communications Technology Planning & Evaluation (IITP) showed the project’s shift from individual chip development to system integration. Rebellions, Moreh, the Electronics and Telecommunications Research Institute (ETRI) and other K-Cloud participants attended.

From chip benchmarks to system integration

Earlier work focused on the performance and power efficiency of individual chips. The new phase adds software-based allocation and consolidation of chips specialized for inference, training, memory and networking.

HyperAccel handles large language model (LLM) inference semiconductors, while Rebellions leads training-NPU development. Companies developing CXL-based memory, DPUs and resource-scheduling software also participate, with the shared goal of operating different domestic AI semiconductors in one data center.

HyperAccel CEO Joo-Young Kim said: “Existing AI data centers have CPUs and GPUs combined in the same server and operate with static resource allocation, which leads to low utilization.”

He added: “Our goal is to build a composable cluster that configures domestically made AI semiconductors as disaggregated resources and dynamically allocates them according to incoming jobs.”

A composable cluster treats inference chips, training chips, memory and network devices as independent resources, then combines them as needed. Unlike a fixed server configuration, it can direct compute according to workload and AI-model requirements.

What does this change for data-center operators?

The project now evaluates resource utilization through system-level validation rather than chip benchmarks alone. If the integrations hold, software can allocate compute and pooled memory to actual workloads; if they do not, a high-performing NPU may remain unsuitable for a working data center.

Three-year integration path

• Year 1: HyperAccel developed a hardware simulator for inference semiconductors.
• Year 2: HyperAccel advanced a multi-compute-core architecture and fabricated an actual chip.
• Rebellions: The company built a single-node environment with multiple NPUs, then developed a multi-node distributed training environment based on remote direct memory access (RDMA), a cross-node memory-access method.
• Year 3: Participants plan to install multiple NPU and DPU types in one server and verify that they operate together.
• Next stage: The project will configure inference chips, training chips and CXL memory as separate resource pools, then use software to assemble the required compute at data-center scale.

Mixed-chip software must preserve results

Squeezebits identified the central consistency risk at the event: training the same AI model on a GPU and an NPU can produce different results because compute precision and execution order differ.

Small computational errors can compound during training, altering model weights and final performance. As the use of reinforcement learning (RL), where inference generates answers and training updates the model, expands, those stages can run on different semiconductors. Matching computational results therefore becomes more consequential.

Squeezebits built a simulator that reproduces NPU computing characteristics on a GPU and verified 16 major operations. The company also began building benchmark training datasets from open AI models.

Its next test will compare training results on Rebellions’ actual NPU to identify errors that emerge when different semiconductors work together.

Bertha enters service validation

• Samples and PoC: HyperAccel obtained engineering samples of its Bertha inference semiconductor in March, completed hardware bring-up and software installation, and is conducting an initial proof of concept (PoC), a limited implementation test, with Naver Cloud.
• Server scale: The company is developing servers that can install up to eight Bertha cards and is seeking partnerships for large-scale systems.
• Memory: HyperAccel secured about 200 LPDDR5X samples from Samsung Electronics for work on next-generation low-power dynamic random access memory (DRAM). It is producing new boards and aims to load software and demonstrate the system around February next year.

Bertha and Nvidia split the workload

HyperAccel is also developing a mixed configuration in which Bertha handles prefill, the stage where an AI model processes its input context, while an Nvidia GPU handles decode, the stage that generates an answer.

Simulations indicated the potential to raise overall throughput by up to three times. That figure comes from simulations rather than production measurements, and HyperAccel plans to continue related system development through year-end.

Commercialization moves to the system level

K-Cloud now treats software compatibility and system integration as commercialization requirements alongside chip performance and power efficiency. Participants say an individual NPU offers limited value if it cannot operate reliably with other semiconductors in an operating data center.

HyperAccel and Rebellions plan to address that constraint through system integration and validation, extending the domestic AI-chip program from component benchmarks to full data-center operation.