Google Adds TPU 8tx and 8i Max: Confidential Computing and 17.2 TB/s

Google has shipped four distinct TPU system configurations in a single year for the first time. The two new arrivals, the TPU 8tx and the TPU 8i Max, are not new chip designs. The 8tx reuses training silicon to deliver confidential computing on custom 5th Gen AMD EPYC "Turin" hosts. The 8i Max fuses two 8i chips into one package and doubles HBM bandwidth to 17.2 TB/s.

That pairing matters for the market. AMD has now landed EPYC inside a non-AMD accelerator system at a major hyperscaler, and it has proven its confidential computing credentials in the process. Nobody expects an overnight 10-point server CPU market share jump. It is a strategic win.

What does the 8tx change for regulated users?

The TPU 8tx targets regulated enterprises and governments running frontier or proprietary models alongside sensitive data. It uses the same silicon as the training-focused TPU 8t. The difference sits in the host layer: Google paired the accelerators with custom dual-socket 5th Gen AMD EPYC Turin CPUs.

Normally, data stays encrypted at rest and in transit but must be unlocked in memory while the machine processes it. That window is where confidential computing steps in. The 8tx encrypts data in use inside an isolated trusted execution environment, so active data never sits exposed in system memory.

The engineering logic behind the CPU choice is concrete. The TPU 8t exposes a PCIe Gen5 x16 interface. A dual-socket Turin configuration supplies 128 Gen5 lanes, which means zero I/O oversubscription across four TPUs plus high-speed NICs. Google also noted that a Gen6 host such as AMD EPYC Venice would step down to Gen5 speeds without adding accelerator bandwidth, so it fits their 2027 hardware qualification schedule to stay with Turin for now.

Google's board rendering shows the physical layout: four accelerator chips with heat sinks and connector ports along one edge, forming the tray that pairs the TPUs with their Turin host CPUs.

Why did Google switch the 8tx to Boardfly networking?

The 8tx adopts the Boardfly network topology from the inference-oriented TPU 8i rather than the training-optimized torus. The numbers explain the trade. Boardfly has a maximum network-hop diameter of seven, versus sixteen hops in the torus design. Fewer hops mean lower latency, which matters for real-time reasoning.

This matters most for multi-step agents that make many sequential inference calls. Google claims up to 2x lower latency than the TPU 8t with a near-zero performance penalty. The structural difference in hop count is why Google keeps tailoring interconnects to workloads instead of relying on a single fabric.

What does the 8i Max solve?

The TPU 8i Max attacks the memory wall from a different angle. When many agents work across an entire codebase or hours of video at the same time, memory bandwidth becomes the bottleneck before compute does. Google's answer: combine two low-latency TPU 8i chips into a single multi-chip package.

The resulting specifications:

• 384 GB of high-bandwidth memory, roughly a third more than a single TPU 8i
• HBM bandwidth doubled to 17.2 TB/s
• On-chip SRAM doubled to 768 MB
• Compute and SRAM both doubled versus a single 8i chip

Those numbers directly address the memory wall that bottlenecks large-context agentic workloads.

Which system should a workload use?

We asked, and Google gave a clear rule. If data must remain within the confidential computing domain, users should stick with the TPU 8tx for inference and serving. The 8tx retains the same low-latency Boardfly topology optimized for real-time tasks, so confidential workloads do not pay a latency price for the isolation.

What is the takeaway?

Google is now tailoring TPU offerings to different parts of the AI stack, and effectively to different customers. The 8tx reads as a customized product built for confidential computing deployments. The 8i Max is built for inference at scale, doubling memory resources where agent workloads hit their ceiling.

For AMD, the 8tx is the quieter but arguably more significant story. EPYC won a socket in a non-AMD accelerator platform at a hyperscaler, and AMD demonstrated confidential computing capability at production scale. That combination counts for more than any single design win's unit volume.