Test report DSG-1447 · Rev D · tested November 12, 2026

Processors & AcceleratorsDevice under test

Four AI Chip Camps in November 2026: What the Numbers Say

Google's November 9 TPU 8tx and 8i Max announcement leaves buyers across four chip camps. AMD posted $8.5 billion data-center revenue, up 97 percent, while most data-center chips remain price-unlisted.

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Amara Osei

Spec summary

  1. Google announced TPU 8tx and TPU 8i Max on November 9, 2026; availability points to 2027
  2. AMD reported record Q3 2026 data-center revenue of $8.5 billion, up 97 percent year over year
  3. AWS plans 2 million additional Blackwell Ultra, Rubin and Rubin Ultra GPUs across 2027 and 2028
  4. AMD MI355X ships with 288GB HBM3e per GPU; a complete eight-GPU server example costs $590,000
  5. Apple M5 Ultra Mac Studio supports up to 512GB unified memory at 1.2TB/s bandwidth
GPU vs TPU vs NPU: 4 AI Chip Camps Compared [2026]
Fig. AGPU vs TPU vs NPU: 4 AI Chip Camps Compared [2026] — moebiusdream / pixabay

On November 9, 2026, Google announced two new TPU variants, the TPU 8tx and TPU 8i Max — neither shipping, both pointed at 2027 availability. That announcement leaves buyers in November 2026 choosing among four live camps: Nvidia GPUs, Google TPUs, AMD Instinct accelerators, and the NPUs embedded in Apple and Qualcomm silicon.

Each camp answers a different question. GPUs remain the general-purpose default for training and inference. TPUs are Google's custom matrix engines, rentable only through Google Cloud until an Oracle partnership brings TPU capacity to Oracle Cloud Infrastructure starting in 2027. NPUs run small models inside phones and laptops on a power budget. CPUs handle everything around the model.

What does each silicon family actually do?

Nvidia added tensor cores, lower-precision math and the CUDA software stack to the GPU's parallel architecture, making it the default for most AI teams. AMD mirrors the approach with Instinct hardware and the open ROCm stack. TPUs drop the graphics heritage entirely: Google built them around large matrix multiplications and tight inter-chip networking, so thousands behave like one machine.

Apple's Neural Engine and Qualcomm's Hexagon NPU are blocks inside larger chips, not standalone training accelerators. They let a device run a language model or transcription model without draining the battery or sending data to a server.

The CPU has also returned to the AI conversation in 2026. Agentic workloads spend much of their time in tool calls, orchestration and retrieval — none of which a matrix engine accelerates.

Where do the specs stand as of November 12, 2026?

  • Nvidia: Blackwell is now the prior data-center generation but remains active; Vera Rubin debuted in MLPerf Inference v6.1 in September 2026 and reportedly shipped in the second half of the year. An AWS announcement plans 2 million additional Blackwell Ultra, Rubin and Rubin Ultra GPUs across 2027 and 2028.
  • AMD: Instinct MI355X ships in 8-GPU servers with 288GB of HBM3e per GPU; Helios rack production is scaling in Q4 2026. Q3 data-center revenue hit a record $8.5 billion, up 97 percent year over year.
  • Google: Ironwood (TPU v7x) is the production platform. Google claimed the April-announced TPU 8t superpod reaches 9,216 chips' worth of scale — 9,600 chips, roughly 121 exaflops and 2 petabytes of shared memory — and nearly 3 times prior-generation compute. No independent test has confirmed these figures.
  • Apple: The M5 Ultra Mac Studio supports up to 512GB of unified memory at 1.2TB/s bandwidth; Apple claims up to 4.3 times the performance of the M3 Ultra model. The M6 MacBook Pro starts at $1,999.

Pricing remains mostly opaque. Nvidia publishes no data-center prices; one retailer listed the RTX PRO 6000 Blackwell Workstation Edition at $14,079.99 in early November. Google points customers to a pricing calculator, and AMD's November 9 example priced a complete eight-GPU MI355X server at $590,000.

How should buyers read vendor benchmarks?

Treat every vendor benchmark as a claim until a third party reproduces it. Apple compares to its own last chip. AMD compares to Nvidia's unshipped Rubin generation — claiming the MI455X and MI430X offer 50 percent more memory capacity and 6 percent higher peak memory bandwidth. Google compares to its previous generation. Check precision labels (FP4, MXFP4, NVFP4, FP8 and BF16 are not interchangeable), distinguish peak theoretical figures from measured MLPerf results, and check who ran the test.

Nvidia's November 6 developer blog reported up to 1.62 times faster text-to-image generation with NVFP4 than BF16 on a single B200. Those are Nvidia's own numbers, but they show where Blackwell pulls ahead.

What real deployments show

Six deployments from vendor and customer statements divide the work. Nvidia's Solstice supercomputer is planned with 100,000 Blackwell GPUs. Biotech firm Absci bought an MI300X cluster from Oracle Cloud Infrastructure on October 19 for antibody design. A Google Cloud case study published November 11 described an EU customer waiting for Ironwood regional availability. Apple's Secure Exclaves run isolated inference on the Neural Engine for health and home sensing. AMD, Supermicro and Spectro Cloud published an enterprise stack claiming up to 75 percent lower total cost of ownership — an AMD figure with footnotes.

For most teams, the GPU remains the default, with Nvidia Blackwell the safest option: strongest third-party results, deepest software support, broadest availability. TPUs win when scale and Google Cloud residency align. AMD is the credible second source. NPUs compete on a different axis — they decide where a model runs, not how fast it trains.

The pattern across all camps is consistent: frontier training on GPUs, scale-out inference on GPUs and TPUs, private inference on NPUs, and every deployment still needs CPUs.

via shattered.io (Source)

Filed under

  • ai-accelerators
  • nvidia-gpus
  • google-tpu
  • amd-instinct
  • npus
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Amara Osei

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Staff writer covering money, funding and market shifts around hardware layer of artificial intelligence at Die Signal.

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