ETH Zurich and New York University have released a research paper on the characterization of HBM power consumption, published via Semiconductor Engineering. The study addresses a measurement gap that has grown urgent as AI accelerators shift their power budgets toward memory.

High-bandwidth memory now sits at the center of accelerator design. Each new generation of HBM stacks more dies and more signal lines into the same footprint, and every additional layer draws current. That current is hard to measure directly, because the memory sits on the same package as the compute silicon it feeds.

What does the study cover?

The researchers characterize how HBM consumes power across operating conditions. Their institutions, ETH Zurich and NYU, have both published prior work on memory systems and accelerator architecture. The paper appears in Semiconductor Engineering's research digest, which tracks academic work relevant to chip design.

The core problem is simple to state. Accelerator vendors quote total package power, but designers need to know how much of that budget the memory consumes and when. Without that breakdown, engineers cannot optimize the trade between bandwidth and energy. A characterization method that isolates HBM draw gives them that number, and lets them compare memory generations on equal terms.

Why does this matter now?

HBM demand has scaled with large-model training. Memory bandwidth, not raw compute, limits many inference workloads. That makes memory power a first-order design constraint rather than a footnote in the datasheet.

The practical questions follow directly:

• How much power does an HBM stack draw at idle versus full bandwidth?
• How does consumption change with temperature and stack height?
• Can designers predict memory power from workload traces alone?

Answers to these questions shape decisions worth billions in data-center operating cost. A single percentage point of memory efficiency, multiplied across large GPU fleets, translates into measurable energy savings.

What does this change for engineers?

For accelerator and system architects, a published characterization method offers a reference point. Teams can validate their own power models against independent measurements instead of relying on vendor figures. For memory vendors, the work adds external scrutiny to specifications that customers increasingly question.

The study also matters for tooling. Power simulators need accurate per-component models, and memory has often been the weakest link in those models. Better characterization data feeds directly into better simulation, which shortens design cycles.

The wider context

Academic scrutiny of memory power arrives as the industry debates HBM roadmaps. Stacks are moving to more layers and higher signaling rates, and both changes raise current draw. Independent measurement lets buyers compare claims across suppliers.

ETH Zurich and NYU bring complementary strengths to the problem: one institution with deep memory-systems research, the other with extensive accelerator and machine-learning systems work. The joint publication signals that memory power characterization has become a shared concern across the compute stack, not a niche topic for DRAM specialists alone.

Readers who want the full methodology should consult the paper directly through Semiconductor Engineering's research listing, where the teams describe their measurement setup and report their findings in detail.