DDR5 server memory costs 9X to 13X more per gigabyte than it did in November 2022, when OpenAI's ChatGPT triggered the generative AI boom. That single data point captures a structural shift: memory has displaced compute as the control point of the IT industry, and the price curves prove it.

Gartner's latest chip revenue breakdown shows the semiconductor market nearly doubling between 2025 and 2026, with flash counted as memory. Forecasts indicate the growth rate decelerating between 2026 and 2027 — an outcome many analysts considered inevitable once the GenAI capacity race peaked.

How much did memory prices actually move?

The street-price numbers from November 2022 to late 2026 tell the story:

• DDR4 server memory: roughly $3 per GB then, now 2X to 3X higher
• DDR5 server memory: roughly $4 per GB then, now 9X to 13X higher
• 30 TB TLC enterprise SSD: 10-13 cents per GB then, now 6X to 7X more
• 30 TB nearline disk drive: about 2.5X more over the same span

Part of the increase reflects recovery from the late-2021 memory and flash price crash caused by oversupply. The rest reflects scarcity: memory makers are shifting DRAM capacity to HBM production for AI accelerators, chasing higher revenues even where profits do not follow.

Cheap disk is not an escape route. The hyperscalers and cloud builders have contracted the vast majority of supply from the three remaining drive makers — Seagate, Western Digital, and Toshiba.

What does HBM cost, and who pays it?

HBM pricing is murkier because the market is closed. Samsung, SK Hynix, and Micron Technology are the only makers, and they sell to GPU and XPU vendors under contract, with no spot prices.

The rumored price history: HBM2 debuted in 2017 at around $20 per GB, settling to about $8 per GB by 2019. HBM2E ran around $10 per GB, HBM3 around $12, and HBM3E around $13.50. HBM4, which ships in the next GPU and XPU generation, is rumored at around $16 per GB — specifically, Nvidia's contract price is said to be $560 to $600 per 36 GB stack.

Some expect HBM4E, with a substantial bandwidth bump, to cost twice as much per GB. That does not fit the trend data. Twenty dollars per GB is plausible; thirty-six is not, even with the benefits.

The key figure: finished HBM cost per GB has risen only 1.6X since the GenAI boom started, while manufacturing yield losses grow with each generation. HBM makers reportedly plan to raise HBM4E prices in 2027 to bring HBM profitability in line with standard DRAM.

How are GPU and XPU designers responding?

End users pay far more than those contract prices. HBM likely represents half the cost of an Nvidia or AMD GPU to the buyer, and closer to 65 percent of the cost of an XPU accelerator from hyperscalers, cloud builders, or AI model builders — a group that now includes OpenAI with its "Jalapeno" accelerator.

Faced with allocation limits, vendors are making hard trade-offs:

• Some stick with more HBM3E stacks instead of moving to HBM4, keeping bandwidth for inference decode while sacrificing capacity
• AMD holds at 488 GB for its "Altair" MI455X accelerator
• Nvidia is said to be considering as low as 192 GB on some future Rubin and Rubin Ultra designs, backing away from the original "Rubin Ultra" plan of four reticle-limited chiplets and up to 1 TB of HBM4E

The more likely path: moving the HBM controller off the GPU chiplet and onto a customizable base die, enabled by HBM4 and HBM4E designs. Nvidia calls this NVHBM, but the technique is not exclusive to Nvidia, and others will embed mathematical functions in the base die — the processor-in-memory approach that has existed for a decade without market traction.

Nvidia quantified the benefit: "By integrating the memory controller into the 3D HBM stack instead of the XPU, NVHBM delivers up to 30 percent greater memory bandwidth and 15 percent lower HBM power consumption, and frees up to 25 percent more area on XPU compute die compared with standard HBM4E."

A plausible Rubin Ultra outcome uses that freed die area across two chiplets: 256 GB (eight-high stacks), 384 GB (twelve-high), or 512 GB (sixteen-high) at 28 TB/sec of bandwidth, versus the original four-chiplet design's 1,024 GB and 58 TB/sec. Every GPU and XPU maker faces the same calculus — maximum capacity and bandwidth on leading-edge process, at a far lower price per GB.