Microsoft's Maia 300 and Intel's next AI silicon point to two different memory technologies, HBM4 and LPDDR5X respectively, according to a TrendForce report. The split marks a structural fork in how AI accelerator vendors plan to feed data-hungry chips through 2026 and beyond.

The divergence matters for the memory supply chain. HBM (high-bandwidth memory, stacked DRAM placed on the same package as the processor) has dominated the AI accelerator market to date. LPDDR5X (low-power double data rate memory, the type used in phones and laptops) costs far less per gigabyte but delivers lower bandwidth per stack.

What does Microsoft's choice change?

Microsoft's Maia 300, the successor to its in-house Maia 100 accelerator, appears configured around HBM4, the next generation of the high-bandwidth standard. That choice would add a major hyperscaler to the HBM4 demand queue alongside established buyers. TrendForce frames Microsoft's design as a driver of HBM4 demand growth.

HBM4 raises the interface width from HBM3's 1,024 bits to 2,048 bits per stack. Wider interfaces push vendors toward larger package substrates and tighter thermal budgets. Every bandwidth promise here carries a cost caveat: HBM remains the most expensive memory per bit in production.

Why is Intel betting on LPDDR5X?

Intel, by contrast, is pairing its AI silicon with LPDDR5X, per the report. The logic is economics. LPDDR5X offers a lower total cost of memory for inference workloads that tolerate lower peak bandwidth, and it draws less power per transfer than HBM. Intel has used this argument before.

What TrendForce does not say is equally notable. The report gives no capacity figures, no named Intel product, and no timeline for volume shipments on either side. Without those numbers, the demand projections rest on design intent rather than confirmed orders.

How should buyers read the split?

Two takeaways for procurement and design teams:

• HBM4 demand now has a hyperscaler anchor in Microsoft, tightening an already constrained supply base dominated by SK hynix, Samsung and Micron.
• LPDDR5X validation by Intel keeps a lower-cost memory path alive for inference-first accelerators, a hedge against HBM price escalation.

The comparison that matters: HBM4 is to LPDDR5X roughly what a dedicated freight rail line is to a highway — higher throughput per channel, at far higher fixed cost. Vendors choosing between them are betting on workload mix, not on a single winner.

TrendForce's framing implies both camps can coexist. That is plausible. It is also convenient for memory makers, who sell into both camps regardless of which architecture wins design slots.

What remains unverified?

Several questions stay open. TrendForce does not publish Maia 300 shipment volumes, HBM4 stack counts per package, or Intel's launch dates. Microsoft has not publicly confirmed the Maia 300's memory configuration. Until vendors state configurations on the record, treat the HBM4-versus-LPDDR5X split as directional intelligence, not settled fact.

The report's core signal still stands. AI memory demand is fragmenting by workload economics, and the memory suppliers hold pricing power in every branch of that fork.