Test report DSG-9554 · Rev A · tested October 30, 2026

Processors & AcceleratorsDevice under test

Microsoft’s Maia 300 brings 288GB HBM4 per chip to OCP 2026

Microsoft showed the Maia 300 at OCP 2026: eight HBM4 stacks, 288GB, 18TB/s memory bandwidth, a four-accelerator node and a stated path to 96 chips per rack.

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Grace Kim

Spec summary

  1. Maia 300 offers 288GB of HBM4 across eight stacks and 18TB/s memory bandwidth.
  2. The accelerator provides 3.2TB/s bidirectional scale-up bandwidth and carries a 950W TDP.
  3. Microsoft displayed a four-accelerator node and says 96 Maia accelerators fit in one rack.
  4. Microsoft targets roughly 12,000 accelerators within a scale-up domain.
  5. OCP 2026 followed Microsoft’s Maia 200 deep dive at Hot Chips 2026.
Microsoft Maia 300 Shown at OCP 2026
Fig. AMicrosoft Maia 300 Shown at OCP 2026 — PIRO4D / pixabay

By Grace Kim

Microsoft’s in-house Maia 300 AI accelerator delivers 288GB of HBM4 (high-bandwidth memory, generation four) across eight stacks, with 18TB/s of memory bandwidth and 3.2TB/s of bidirectional scale-up bandwidth, Microsoft said at OCP 2026.

The next-generation chip followed Microsoft’s Maia 200 deep dive at Hot Chips 2026, held a few weeks earlier. At the larger OCP Summit 2026, Microsoft’s booth showed the Maia 300 as a complete four-accelerator node rather than as a bare chip, exposing the system’s cooling, power and interconnect design.

Before the show, I shared an Uber ride from the hotel to the convention center with Microsoft’s project manager for Maia 300 and promised coverage of the platform. The resulting display supplied a node-level view that a chip alone would not.

From chip to rack

Microsoft says 96 Maia accelerators fit in one rack and roughly 12,000 can sit within the scale-up domain, the connected set of accelerators. The four-accelerator enclosure therefore functions as a building block for Microsoft’s stated rack and domain configurations.

An overhead stock photograph shows the node’s board and cable arrangement. The image also serves as the basis for the report’s identification of components that Microsoft did not label.

Cooling, power and scale-up links

Each accelerator carries a 950W TDP (thermal design power) rating and sits beneath a liquid-cooled cold plate. The chassis does not use liquid cooling throughout: its CPU, SSDs, OCP NIC 3.0 (network interface card) devices and many components around the accelerators are cooled by a large fan partition spanning the enclosure.

At the rear, the node connects to a busbar (power-distribution bar), blind-mate liquid-cooling connections and its scale-up network.

The overhead stock image shows what appear to be MCIO x16 connectors and numerous cable connections. The report’s best guess was UltraPass connectors, which help scale within the node. The board also uses a PCIe (Peripheral Component Interconnect Express) topology and extensive fabric connectivity throughout the chassis.

This is a cable-heavy design. The report contrasts it with NVIDIA’s Vera Rubin NVL72 nodes and infrastructure, which NVIDIA is designing around fewer cables. Each Maia accelerator sits on its own PCB (printed circuit board) with multiple cables, and the system contains many such boards.

The enclosure is about 1.5 times standard OU (rack-unit) width, but remains narrower than the double-wide AMD Helios. Because Microsoft designs the ASICs (application-specific integrated circuits), it may also customize the racks to accommodate the chassis.

What does the Maia 300 change for AI infrastructure?

For infrastructure planners evaluating Microsoft’s platform, the practical change is the node specification: 288GB of memory and 18TB/s of bandwidth per accelerator, four chips in the displayed enclosure, and a stated path to 96-chip racks. Planners must also accommodate mixed liquid-and-air cooling and dense cabling rather than a uniformly liquid-cooled, low-cable chassis.

Microsoft’s scale-up domain target of roughly 12,000 accelerators raises the system-design stakes beyond the board. At OCP, the emphasis moved from Maia 200’s chip-level deep dive to the physical node, where power delivery, coolant distribution and interconnect density determine how the stated capacity can be assembled.

An earlier Microsoft Azure HBv4 system with AMD EPYC Genoa processors used a custom-designed heatsink. Its components were described as carrying well over 4kW of TDP, while each rack held 24 trays.

A separate possibility raised in the report was a DGX Station-style tower built around Maia 300. Gigabyte and MSI systems served as examples, and a Supermicro review was due the following week. Such towers carry six-figure prices; the account stated that, “from what I have heard, demand is crazy.”

That configuration would depend on Microsoft building a developer ecosystem and selling Maia, potentially at a lower price point. The report treated the desktop scenario as hypothetical rather than an announced Maia 300 product.

via ServeTheHome (Source)

Filed under

  • microsoft-maia-300
  • ai-accelerators
  • hbm4
  • scale-up-networking
  • ocp
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Grace Kim

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Market editor covering regulation, policy and their impact on hardware layer of artificial intelligence at Die Signal.

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