Test report DSG-3188 · Rev C · tested October 10, 2026

Foundries & ManufacturingDevice under test

TSMC to deploy High-NA EUV lithography in 2030 on A10 or A11 nodes

TSMC will introduce High-NA EUV lithography in 2030 on its A10 or A11 process nodes, the company has confirmed. The timeline places the Taiwanese foundry several years behind Intel in adopting ASML's $380 million High-NA EUV scanners.

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Spec summary

  1. TSMC plans to introduce High-NA EUV lithography in 2030
  2. A10 and A11 technology nodes are the prime candidates for first production use
  3. High-NA EUV operates at 0.55 numerical aperture, up from 0.33 in current EUV tools
  4. ASML's TWINSCAN EXE:5000 High-NA system costs roughly $380 million per unit
  5. Intel installed the first commercial High-NA EUV tool at its D1X fab in Hillsboro, Oregon, in 2024
TSMC to start using High-NA EUV lithography in 2030 — A10 or A11 technology prime candidates for use - tomshardware.com
Fig. ATSMC to start using High-NA EUV lithography in 2030 — A10 or A11 technology prime candidates for use - tomshardware.com — AI-generated

Taiwan Semiconductor Manufacturing Company plans to introduce High-NA EUV lithography in 2030, with the A10 and A11 technology nodes identified as the prime candidates for first production use. The timeline would place TSMC several years behind Intel, which received its first High-NA EUV scanner from ASML at its D1X fab in Hillsboro, Oregon, in 2024.

What is High-NA EUV?

High-NA EUV refers to extreme ultraviolet lithography scanners operating at a numerical aperture of 0.55, up from 0.33 in current production EUV tools. The higher aperture enables finer resolution and supports continued shrinkage of transistor features below the limits of standard EUV. ASML's TWINSCAN EXE:5000 is the only commercially available High-NA system, with each unit priced at roughly $380 million.

Why the 2030 timeline matters

TSMC's cautious stance reflects three constraints: tool cost, ongoing yield maturity work at ASML, and the productivity gap versus the installed base of low-NA NXE systems. The EXE:5000 is documented at approximately 150 wafers per hour in early operation, well below the 175 wafers per hour or higher achieved by mature low-NA NXE:3800E tools.

Which nodes are in scope?

The A10 designation would place the node at the 1-nanometer (10-angstrom) class, with A11 representing the next shrink. TSMC rebranded its process naming from N-nm to A-angstrom labels starting with the A16 node announced in 2024. The foundry's current production frontier is the N3 family, with N2 in risk production during 2024.

How does the competition stack up?

  • Intel: High-NA EUV tool installed at D1X in 2024, in use for Intel 18A and 14A development
  • Samsung: Has evaluated High-NA systems; has not committed to a production date
  • TSMC: First High-NA production use targeted for 2030, on A10 or A11

What changes for customers?

Chip designers working on A10 and A11 tape-outs will be the first TSMC customers to access High-NA-patterned layers. The transition carries a cost premium tied to tool price and throughput delta. Per-wafer cost increases are likely on the first nodes, with pricing expected to ease as tool productivity improves in successive generations.

What's still unclear

TSMC has not disclosed how many High-NA tools it intends to order, nor the share of critical layers that will move to the new platform. The foundry has signalled it will deploy High-NA only where the resolution benefit outweighs the productivity penalty — a posture consistent with its measured adoption of standard EUV starting in 2019.

via Google News: TSMC (Source)

Filed under

  • tsmc
  • high-na-euv
  • lithography
  • asml
  • process-nodes
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Elena Vasquez

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Senior reporter covering industry trends and analytics at Die Signal.

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