TSMC booked third-quarter revenue above $46 billion, the highest quarterly figure in the company's history as a pure-play contract chipmaker, according to a GuruFocus summary of the Taiwan-based foundry's earnings release.

The topline eclipses TSMC's prior quarterly records by a wide margin and reflects sustained pull from the leading-edge process nodes the company manufactures for fabless chip designers. The Q3 print positions the Hsinchu-headquartered firm to close calendar 2025 well ahead of its prior-year financial benchmarks.

What does the milestone cover?

• TSMC's fiscal Q3 ends September 30, with the headline result typically posted in mid-October.
• The figure aggregates wafer fabrication, advanced packaging, and related foundry services.
• Quarterly revenue is reported in New Taiwan dollars, converting to roughly $46 billion-plus at prevailing FX rates.
• The full disclosure, including segment splits and 2026 capex guidance, generally follows within ten weeks of the release.

How does the pure-play foundry model work?

TSMC manufactures chips designed by customers such as Apple, Nvidia, AMD, Qualcomm, and Broadcom, retaining no equity in the silicon it produces. The asset-light separation lets the foundry concentrate capital spending on fabrication tools — chiefly extreme-ultraviolet (EUV) lithography systems from ASML — while customers own architecture, marketing, and end-product integration.

What sits behind the technology lead?

The foundry's moat sits at the leading edge of process scaling. TSMC began high-volume production of its 3 nm (N3) family in late 2022 and shipped N3E and N3P variants through 2024. Its 2 nm (N2) node entered risk production in 2025, with volume ramp scheduled for the second half. The N2 platform adopts a gate-all-around (GAA) transistor architecture — the same shift that foundry competitors Intel (18A) and Samsung Foundry (SF2) have positioned for their next nodes.

What is driving the Q3 topline?

Three demand vectors have dominated 2025 booking trends:

• AI accelerator silicon for hyperscale data centers, primarily Nvidia's Blackwell family and AMD's MI series.
• Smartphone system-on-chips for the annual iPhone refresh cycle and competing Android flagships.
• High-performance compute for automotive ADAS platforms, where TSMC has expanded 5 nm and 3 nm allocations.

Advanced packaging — particularly CoWoS variants used to assemble AI GPUs and HPC parts — has been the dominant capacity bottleneck in 2025, supporting pricing power and utilization at the leading-edge fabs.

What risks does the record print flag?

• Geopolitical exposure: most of the manufacturing footprint remains concentrated in Taiwan, with offset capacity in Arizona and Japan still scaling.
• Node transition risk: 2 nm ramp carries first-generation yield uncertainty relative to mature 3 nm lines.
• Customer concentration: the top-10 customer cohort represents a clear majority of revenue.
• FX translation: material strengthening of the New Taiwan dollar against the US dollar compresses USD-reported revenue without affecting underlying NTD performance.
• Tool supply: ASML's EUV system lead times remain the binding capacity constraint at the most advanced nodes.

What is the market footprint?

TSMC's underlying common stock trades on the Taiwan Stock Exchange under ticker 2330. American depositary receipts trade on the New York Stock Exchange under ticker TSM. The company operates a single global fab network, anchored by facilities in Hsinchu, Tainan, and Taichung, with newer capacity in Phoenix, Arizona and Kumamoto, Japan.

Management has not yet disclosed segment-by-segment revenue, capacity utilization rates, or the 2026 capex envelope. Those figures typically appear in the company's full quarterly press release and earnings call transcript.