Test report DSG-5861 · Rev B · tested September 30, 2026
Edge AI SiliconDevice under test
TI MSPM0G5187 MCUs Pair TinyEngine NPU with Cortex-M0+ for Edge AI
TI's MSPM0G5187 MCU combines an 80 MHz Cortex-M0+ core with a TinyEngine NPU rated at 2.56 GOPS, targeting edge-AI inference, sensing and control. Now available from Mouser Electronics.
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- Amara Osei
Spec summary
- MSPM0G5187 integrates a TinyEngine NPU rated at up to 2.56 GOPS at 80 MHz, supporting 8-, 4-, and 2-bit weights and 8- and 4-bit data
- The MCU provides up to 128 KB ECC flash in two banks with address-swap support and up to 32 KB SRAM with ECC or hardware parity
- Peripherals include a 12-bit 1.6-MSPS ADC with 26 external channels, a high-speed comparator with 8-bit DAC, 12-channel DMA, and USB 2.0 full-speed with integrated PHY
Texas Instruments' MSPM0G5187 mixed-signal microcontrollers are now available from Mouser Electronics. The parts pair an Arm Cortex-M0+ core with an integrated TinyEngine neural processing unit (NPU), targeting edge-AI inference, sensing, and control applications.
The device operates at up to 80 MHz. It provides up to 128 KB of embedded flash memory with error correction code (ECC) and up to 32 KB of SRAM with ECC protection or hardware parity. TI organizes the flash into two main banks with address-swap support, which enables field firmware updates without interrupting operation.
NPU specifics
The TinyEngine NPU is a hardware accelerator built for machine-learning inference, with a focus on deep convolutional neural networks. TI specifies up to 2.56 GOPS at 80 MHz. The accelerator supports 8-, 4-, and 2-bit weights and 8- and 4-bit data, giving designers flexibility on model size versus precision.
The NPU runs autonomously from the main CPU. It supports convolutional, pointwise, depthwise, pooling, and residual neural-network layers. TI lists target applications including time-series classification, arc-fault detection, motor-fault detection, and electrocardiogram processing. The company also publishes an application note that addresses edge-AI implementations on the MSPM0G5187.
Mixed-signal peripherals
TI combines the NPU with mixed-signal peripherals aimed at sensing and control. The MCU integrates a 12-bit, 1.6-MSPS analog-to-digital converter (ADC) that supports up to 26 external channels. A high-speed comparator includes an integrated 8-bit reference digital-to-analog converter (DAC). The device also carries a 12-channel direct memory access (DMA) controller and flexible timer peripherals.
Connectivity
For serial connectivity, the MSPM0G5187 offers four configurable UNICOMM serial interface modules. These support combinations of up to three UARTs, two I²C interfaces, or two SPI interfaces.
A USB 2.0 full-speed interface integrates the physical layer, clock source, and termination resistors. It supports host operation and crystal-less device operation, reducing the external bill of materials for USB-connected designs.
A digital audio interface rounds out the peripheral set. It supports I²S, TDM, left-justified, and right-justified formats.
For design engineers working on edge inference at the low-power end of the spectrum, the MSPM0G5187 places quantized CNN acceleration directly on an MCU-class part with the analog front end needed for signal acquisition. More information is available at mouser.com.
via img.militaryaerospace.com (Original)
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