Samsung used Hot Chips 2026 to outline a three-phase plan for filling spare area on HBM4 and HBM4E base dies. Those base dies now ship on Samsung's 4nm logic node instead of a DRAM process. The Korean vendor wants to turn the base die into more than a passive DRAM-to-host bridge.

Why move the HBM base die to a logic node?

HBM stacks multiple DRAM dies on a base die. The DRAM dies connect to each other through through-silicon vias (TSVs), and the base die carries the physical interface to the host compute die over an interposer. Each new HBM generation scales DRAM-to-base-die bandwidth through denser TSVs, but the host-side path is harder. That PHY already consumes most of the base die's area, and adding pins makes the area and power problems worse.

Samsung noted in its presentation that even though each HBM generation improves power efficiency, total memory power keeps climbing. Moving to a 4nm logic process cuts power and adds density, but the base die's footprint must still match the DRAM stack above it. That mismatch leaves a large block of unused silicon.

What does Phase 1 cover?

Samsung's Phase 1 packs two functions onto the base die:

• An integrated memory controller. DRAM is conventionally "dumb" — a host controller handles precharge, bus direction switches, refresh, and scheduling. Samsung wants to relocate that controller onto the base die and swap the standard HBM interface for a custom die-to-die link. Trimming PHY area on both dies creates the headroom.
• An SRAM-based remap table. Today, row and column spares on a DRAM die can only repair defects on that same die. A small SRAM block on the base die could point any spare cell at any defective cell, including defects on neighboring dies.

The endpoint resembles Intel's Sapphire Rapids, where the memory stack natively grasps the CPU's internal mesh protocol. Tradeoff: such HBM locks tighter to one host architecture and complicates multi-sourcing.

What does Phase 2 add?

Phase 2 keeps filling the leftover base die area after the controller lands. Samsung proposes:

• Telemetry sensors for temperature and voltage.
• An on-die test block that generates patterns without a host, lifting yield and coverage.
• External memory PHYs that let the base die act like an IO die and reach past the interposer's capacity ceiling.
• In-memory compute blocks. Each processing element sits close to only its own DRAM region, so it would face NUMA-style penalties without large caches. Format conversion at load time is a plausible use.

What does Phase 3 propose?

Phase 3 stacks HBM on top of a compute die in a package-on-package arrangement Samsung calls zHBM. The pitch: TSVs between stacked dies cost less power and area than 2D PHYs, freeing transistor budget for the host. Thermals are the catch. AMD's Zen 3, Zen 4, and Zen 5 stacked-cache parts all clocked significantly lower than their non-stacked counterparts, and that stack uses only one extra die. HBM stacks many.

What does this mean for HBM supply?

The roadmap reflects the surge in DRAM demand that has reshaped the memory market since 2023. The harder constraint is sourcing: every major GPU and accelerator customer still buys HBM from at least two of the three suppliers. Samsung's Phase 1 features, especially improved on-die RAS and self-test, can ship without host alignment. The custom memory controller and zHBM stack require host buy-in, which means convincing SK Hynix and Micron to back a shared protocol.