Salience Labs is shipping a 32-port optical circuit switch with port-to-port latency under 10 nanoseconds and 200 Gb/sec per lane, the Oxford-Münster spin-out announced. The OC-32M targets AI scale-up fabrics stuck at 72 accelerators per coherent memory domain.

The device launched in March and is ramping. It runs 100 Gb/sec native with PAM4 modulation to deliver 200 Gb/sec effective per lane. Salience plans 64- and 128-port versions next, with the architecture extending to 256 ports.

What makes Salience's switch different?

The startup avoids both incumbent OCS techniques. MEMS mirror arrays, used in Google's Apollo system across the last four TPU generations since 2015, spin tiny mechanical mirrors to make connections. Lumentum markets MEMS gear for AI datacenters in partnership with Nvidia. Coherent uses liquid crystal on silicon (LCoS), also with Nvidia engagements.

Salience uses neither. CEO Vaysh Kewada declined to specify the switching mechanism, but the firm's partnership with Tower Semiconductor for PH18DA III-V lasers and TPS45PH silicon nitride waveguides points to phase-change optoelectronics developed in academic settings.

The company spun from research led by Harish Bhaskaran, professor of applied nanomaterials at Oxford, and Wolfram Pernice, professor of experimental physics at Münster. The OC-32M module combines two chips: a fully integrated silicon photonics OCS plus an amplification and signal conditioning chip, mounted back-to-back on a PCB.

How does latency compare?

By a factor of roughly 25. Salience's port-to-port hop sits under 10 nanoseconds, which the company notes matches main memory speed. The Broadcom Tomahawk Ultra Ethernet ASIC lands around 250 nanoseconds. Other Ethernet switches span 450 to 650 nanoseconds, extending to milliseconds in devices Salience deems unfit for memory-fabric scale-up.

Reconfiguration happens 3X faster than MEMS, Salience claims. MEMS and LCoS devices take milliseconds to relink; the silicon photonics switch flips under 300 microseconds.

Energy per port lands 8X lower than Ethernet switching.

What are AI customers trying to build?

Three workloads, according to Salience. Some buyers want to push past Nvidia and AMD's 72-GPU coherent-memory ceiling for AI scale-up. Others seek an alternative to existing rack-scale coherent memory fabrics. A third group targets OCS as the first network layer gluing machines together during GenAI inference decoding.

"We chose to develop OCS because our view is that there was quite a large number of players developing solutions on the CPO, NPO, XPO front, trying to solve the question of how you get data off of the chip and onto the optical fiber," Kewada said.

The thesis: more optical connections inside datacenters means heterogeneous switching, with electrical packet switches and optical circuit switches playing complementary roles.

What performance does Salience claim for scale-up inference?

A modelled 576-GPU machine running Nvidia's Megatron 2T framework boosts tokens per second per user by 80 percent when the scale-up layer uses OCS instead of a dual-system design. The improvement comes mostly from the lower-latency memory fabric.

"Our view is OCS was a market ripe for disruption, because the OCSes that are available today on the market are based off a technology that fundamentally is twenty years old if not older," Kewada added.

Can the form factor keep scaling?

A single 1U chassis holds up to eight OC-32M modules today. Kewada said the company is "doing a lot of work on our core architecture to ensure that we can continue to scale port counts."

The amplification chip addresses silicon photonics' traditional loss problem. "One of the key disadvantages of being in silicon photonics has always been the question of loss," Kewada noted. "We have solved that using an amplification that is our own component design and fabricating it on arrays."