Qualcomm's Snapdragon X2 Elite Extreme delivers 228 GB/s of theoretical DRAM bandwidth on a 192-bit LPDDR5X bus while outpacing AMD's Strix Halo and Nvidia's GB10 on CPU-side throughput.

The 18-core SoC splits twelve 5 GHz "Prime" cores across two 6-core clusters and six 3.6 GHz "Performance" cores in a third. Prime clusters carry 16 MB of shared L2; the Performance cluster carries 12 MB. Qualcomm runs those L2 slices at core clock and skips the mid-level caches AMD, Intel, and most Arm parts still include.

What does intra-cluster performance look like?

L2 latency lands at 20–21 cycles on both cluster types. Two Prime cores in each cluster sit at 22–23 cycles, a likely byproduct of a centralized crossbar and the 5 GHz pipeline depth. Performance cores stay uniform, presumably because their 3.6 GHz clock leaves pipeline headroom.

Each core reaches 32B/cycle in read and write directions, so a single core can do 64B/cycle under read-modify-write. The Performance cluster matches that figure even though its load/store unit serves only two 16-byte accesses per cycle.

The fabric treats each cluster as a single coherency client, shrinking the probe set from 18 cores to six and easing snoop traffic.

How does the fabric compare on DRAM?

Qualcomm provides each cluster a 32B/cycle path to the system fabric — the same width AMD's Strix Halo offers. The Snapdragon path runs at cluster clock, not at a slower FCLK-style 2 GHz, so its CPU-side DRAM read bandwidth exceeds Strix Halo's.

DRAM latency measures 115 ns on the LPDDR5X setup. That is competitive for the standard, though still slower than sub-100 ns typical on desktop DDR5. In a mixed read/write loop the chip hits 68.5% of theoretical bandwidth.

Strix Halo and Nvidia's GB10 sit on 256-bit buses producing 256 GB/s and 273 GB/s respectively, hitting 88% and 81% efficiency. Qualcomm's 192-bit, 228 GB/s bus looks modest on paper but feeds CPU cores more reliably.

How well does the fabric handle contention?

Latency from any CPU core stays below 200 ns even when neighboring threads saturate a cluster's 32B/cycle path. Nvidia's GB10 pushes past 200 ns when Arm X925 cores fight for off-cluster bandwidth. Several AMD designs let bandwidth-heavy threads squeeze latency-sensitive ones.

Under CPU+GPU mixed load, latency climbs toward 350 ns — comparable to Meteor Lake at its worst. Combined throughput peaks at 169.3 GB/s: 94.78 GB/s from CPU, 74.86 GB/s from GPU, or 74.2% of theoretical. Strix Halo delivers 226.08 GB/s combined, GB10 243.05 GB/s.

Qualcomm does not let the GPU starve the CPU. With both hungry, each pulls roughly half. The competitors give the CPU more bandwidth when the GPU is quiet but leave DRAM throughput on the table when both compete.

Why cluster at all?

Performance sits solid because the cluster model caps worst-case latencies near the average latency of a mesh-based server die. One monolithic interconnect for 18 cores would either inflate that average or hurt cache latency for ordinary accesses.

A 192-bit LPDDR5X subsystem producing 228 GB/s looks over-spec for the current Prime/Performance plus Adreno X2 workload. Gerard Williams III told Hot Chips that architectural features can be built "with a vision to enable advances in future designs, even if those features don't deliver a huge benefit for a current product." That logic, applied at chip level, points at a future halo-segment part.

Strix Halo and Intel's Panther Lake currently own halo-mobile. The Snapdragon X2 Elite Extreme reads as warning shot, and as a foundation for something larger on both the CPU and GPU sides.