Nvidia detailed the first concrete checklist a RISC-V CPU must meet to host CUDA at Hot Chips 2026, signaling the GPU compute stack will officially extend beyond x86-64 and aarch64. The talk centers on what a "server-grade CPU and platform" looks like to Nvidia's software team.

The starting point is the RVA23 profile and adherence to RISC-V's server SoC and server platform specifications. Those documents cover RAS (reliability, availability, and serviceability) features, a dedicated security processor, and other baseline server behavior. Nvidia engineers stated that the published profile covers most of what the company needs at the platform layer.

What does Nvidia require beyond the RISC-V profile?

Nvidia added four demands on top of the published server specs:

• ACPI support. Nvidia's software team was unhappy when RISC-V hardware lacked ACPI at the start of the CUDA port. The UEFI forum added RISC-V ACPI support in 2025. The RISC-V Boot and Runtime Services (BRS) specification, ratified that same year, includes ACPI.
• Vector extensions. Nvidia cited predication as the key example. Predication lets the compiler avoid branches and ship tighter loops on RISC-V hardware.
• PCIe coherency. Without it, a CUDA-initiated DMA can read stale DRAM data while modified lines sit in CPU caches. Software would have to invalidate caches manually. The RISC-V server SoC specification only recommends cache coherency; Nvidia wants a guarantee.
• Peer-to-peer PCIe. Without it, device-to-device transfers must round-trip through CPU memory, costing bandwidth and forcing extra synchronization.

Nvidia's full list reportedly spans two pages. The company acknowledged it did not walk through every item and targets a performance level rather than a minimum configuration. From Nvidia's perspective, designing around a lowest-common-denominator baseline would force the company to ship inefficient code.

How does NVLink Fusion extend the same model?

The talk also covered NVLink Fusion, Nvidia's program that lets third parties drop NVLink IP into their own silicon. NVLink Fusion inherits every CUDA requirement and adds support for Nvidia's DOCA and NCCL frameworks, plus a close engineering partnership with Nvidia. The GB10 chip — a Mediatek CPU die linked to an Nvidia GPU over NVLink C2C — serves as the template.

That pathway lets customers pair a custom RISC-V CPU with an Nvidia GPU without buying Nvidia's own CPUs, provided the RISC-V silicon meets the server-grade bar.

Will existing RISC-V boards run CUDA?

Not soon. The requirements rule out the vast majority of today's RISC-V hardware. ACPI support in particular remains a sticking point; on aarch64, ACPI support has been spotty at best even after years of standardization. A 2025-ratified RISC-V ACPI standard would likely need several more years to gain wide vendor adoption.

Nvidia is partnering with SiFive to deliver a working reference. SiFive plans to demo a CUDA-capable RISC-V system at Hot Chips. The example CPU specifications shown suggest a high-core-count server part rather than a hobbyist single-board computer.

The path forward for enthusiasts stays narrow. Nvidia has not announced plans to relax the requirements for PCIe-non-coherent platforms or boards without vector extensions. Workloads heavy on compute relative to data movement could tolerate software-managed cache invalidations, but Nvidia treats PCIe coherency as a standard server feature.

Nvidia's stated goal is a fast, low-risk port. Whether the company will eventually loosen the requirements so a broader range of RISC-V boards can feed Nvidia GPUs remains open.