Test report DSG-9759 · Rev D · tested September 30, 2026
Edge AI SiliconDevice under test
Mobilint to Mass-Produce Second-Gen REGULUS NPU by Year-End
Mobilint ships REGULUS customer samples to about 90 firms, targets year-end mass production and a 4 nm chiplet successor on Samsung's process with SEMIFIVE as design house.
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- Priya Raman
Spec summary
- REGULUS is a 17 mm × 17 mm SoC on TSMC 12 nm with LPDDR4X, Ethernet and USB interfaces; mass production is targeted for year-end after completed QRT reliability verification.
- About 90 companies are evaluating Mobilint products, up from roughly 70 in January, including LG Electronics, POSCO DX, Doosan Robotics and Intellivix.
- The REGULUS successor will use a chiplet architecture on Samsung's 4 nm process with SEMIFIVE as design house; development requires at least 100 billion won, supported by a 70 billion won Series C round.

Mobilint plans to start mass production of its second-generation neural processing unit (NPU), REGULUS, by the end of this year. The company has delivered customer samples to clients, opening the full-scale qualification phase, CEO Dongjoo Shin said at the AI Semiconductor Forum breakfast seminar in Seoul on July 9.
REGULUS customer samples are already sold commercially, Shin told the audience at the Grand InterContinental Seoul Parnas event, and reliability verification with QRT is complete.
"Although mass production has been delayed by three to four years compared with overseas competitors, the timing now aligns with the emergence of the physical AI market where the chip will be deployed," Shin said.
Chip specifications
REGULUS is a 17 mm × 17 mm system-on-chip integrating a CPU, a video codec, NPU cores, an image signal processor and scratchpad memory IP. The device supports Ethernet and USB interfaces, uses LPDDR4X memory and is manufactured on TSMC's 12-nanometer process.
Target applications include smart cameras, AI kiosks, industrial robots and agricultural machinery. Shin said Mobilint has received growing inquiries from customers seeking alternatives to Chinese chips from vendors such as Rockchip.
Customer pipeline grows to 90 firms
Around 90 companies are currently evaluating Mobilint products, including REGULUS, up from roughly 70 at the beginning of the year. The list of potential customers includes LG Electronics, POSCO DX, Doosan Robotics, Kolon Benit, LOTTE Innovate, Shinsegae I&C, Daedong and Intellivix.
Mobilint targets both on-premises and on-device AI systems, running edge AI inference without cloud connectivity. In the global edge AI chip market, the company competes against NVIDIA's Jetson platform, Qualcomm and Hailo.
Efficiency claims
Shin said Mobilint's chips deliver measurable advantages over competing products on cost and power draw.
"Edge AI requires high performance, competitive pricing and power efficiency," he said. "Our chips can reduce customers' capital expenditure (CAPEX) by half, lower operating costs by three to four times and improve power efficiency by five times compared with competing solutions."
He added that edge computing offers lower latency, stronger communications security and higher energy efficiency than cloud-based computing.
Software support as a differentiator
Software compatibility represents a second competitive lever, according to Shin.
"Without broad compatibility, it is impossible to enter the market," he said.
Mobilint's software development kit supports 400 AI models across large language models (LLMs), vision-language models (VLMs) and vision-language-action (VLA) models in commercial production environments. No other global edge AI NPU vendor currently supports VLA models, Shin said, calling the capability Mobilint's unique competitive advantage.
Next chip moves to 4 nm and chiplets
Mobilint has already begun developing a REGULUS successor based on a chiplet architecture and a 4-nanometer process. Developing and commercializing a 4 nm chip requires at least 100 billion won, Shin said. The company recently raised 70 billion won in a Series C funding round to fund the effort.
Samsung Electronics will fabricate the next-generation chip on its 4 nm process, with SEMIFIVE acting as design house.
The chiplet approach packages multiple smaller dies into a single processor instead of using one large monolithic die. As system-on-chip functionality expands, larger die sizes cut into manufacturing yields. Distributing key functions across multiple dies improves yield and provides greater scalability, which lowers the cost risk of moving to advanced nodes.
via cdn.thelec.net (Original)
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