Intel is supplying register transfer level (RTL) code for its Atom CPU technology to RosaicLabs, a Delaware startup incorporated in May 2026 — a first for a company that has never before released CPU-core source descriptions to outsiders. Reuters and SemiAccurate both reported the arrangement, which goes well beyond an architectural license.

Days before the Reuters story, on July 27, 2026, a Linux kernel mailing list post surfaced describing working x86 implementations with 16 and 32 Advanced Matrix Extension (AMX) tile registers. Intel's shipping hardware provides eight. No public source connects the two stories, and the distinction matters.

What is Intel actually giving Rosaic?

RosaicLabs Inc. is led by Amarjit Gill, a semiconductor executive who worked with Intel CEO Lip-Bu Tan to assemble the founding team at Rivos. Reuters reports the team includes other Rivos veterans, among them former Rivos finance chief Amit Parikh.

RTL describes the logic and data movement inside a digital design in a form engineers can simulate, verify, modify and synthesize into physical gates. Intel is not merely granting permission to execute x86 instructions; it is reportedly handing over the source-level description of an Atom design.

Open questions remain. Reuters does not identify:

• the Atom generation involved;
• which cache and interconnect logic is included;
• the target manufacturing process;
• contractual limits on modification and shipping.

An amended July filing reportedly gives Rosaic room to raise a $10 million seed round — enough for a small team, but nowhere near enough to bring a leading-edge processor from blank sheet to mass production. Receiving an existing CPU core lets the startup spend its budget on differentiating features rather than rebuilding an x86 frontend, execution engine, memory-ordering machinery and software stack.

What does the 32-tile AMX mailing-list post say?

Longtime x86 researcher Christian Ludloff wrote the July 27 post. In October 2025, he had relayed a notice on the GNU Binutils and kernel lists that opcode allocations, an E000_xxxx CPUID range and a matching MSR range were already "in active use by a corporate entity other than Intel/AMD."

The technical details of the new post are concrete. Intel's current AMX model provides eight tile registers, each holding up to 16 rows of 64 bytes — 1 KB per tile and 8 KB of total architectural state, documented as palette 1.

• A 16-tile implementation can reuse existing VEX encodings addressing TMM0 through TMM15; the 64-byte TILECFG structure already contains row and column fields for 16 tiles.
• A 32-tile implementation requires EVEX encodings addressing TMM0 through TMM31 and doubles TILECFG to 128 bytes.
• Existing CPUID mechanisms can report the larger tile count, so no new feature flag is required.
• Software assuming a 64-byte TILECFG or 8 KB of state would need a degraded eight-tile mode; the post proposes MSR controls to disable the extra registers.

The tile file grows to 16 KB per hardware thread at 16 tiles and 32 KB at 32 tiles — a large state block for an OS or hypervisor to save and restore on many-core parts. That points to a matrix-focused device rather than a general-purpose server CPU. The post also references AI Compute Extensions (ACE), the cross-vendor successor developed by AMD and Intel through the x86 Ecosystem Advisory Group, whose whitepaper defines eight 512-bit-by-16-row tiles. The 16- and 32-tile modes exceed both AMX and ACE baselines.

Is the mystery x86 vendor Rosaic?

Ludloff wrote that an implementation supporting 16 and 32 tiles "has been running at large scale for some time." That phrase clashes with the timeline: Rosaic was incorporated in May 2026, roughly seven months after the October 2025 opcode notice. A startup receiving Atom RTL is unlikely to have designed, taped out and deployed non-standard x86 silicon at scale that quickly.

Reconciling the timeline requires assumptions. The design could have started inside Intel and moved to Rosaic. "Large scale" could mean simulation, emulation or FPGA instances. Or the 2025 corporation could have been a predecessor entity.

The stories may simply be unrelated. The mailing-list posts never name Rosaic, and Reuters never mentions AMX, ACE or a matrix accelerator. Intel's shipping Atom cores lack the per-core AMX engines of Xeon, so Rosaic would still need to design or obtain the accelerator itself.

Other candidates carry their own contradictions. Zhaoxin, with a legal x86 path through VIA, and Hygon, with AMD-derived lineage and data-center ambitions, both submit compiler and kernel work under their own names. A hyperscaler — Google, where Ludloff previously worked, or Meta, with its Rivos connection — fits "large scale" better, but none has disclosed the x86 license such a chip would need.

What changes for the x86 market?

The confirmed fact stands on its own: Intel is letting an outside company build around its CPU RTL. If the deal becomes a repeatable model rather than a one-off, it changes how Intel monetizes its CPU designs and aligns with its stated plan to offer more IP through Intel Foundry. Combined with an unnamed company publicly reserving new x86 architectural space for matrix compute, the x86 ecosystem is opening in ways it has not in decades.